Electro-thermal Investigation on SOI Accumulation Mode Tri-gate LDMOS

Abstract

An electro-thermal co-optimization has been carried out on silicon-on-insulator (SOI) accumulation mode tri-gate (ATG) LDMOS by TCAD simulation. Internal electric field, temperature distribution, critical heat removal path and the thermal resistance of SOI-ATG LDMOS are investigated, providing deep insights into its self-heating mechanism and thermal-aware design. Besides, the junction depth of source/drain, ambient temperature and boundary thermal resistance are optimized to mitigate the self-heating effect (SHE) in SOI-ATG LDMOS. Furthermore, different trench dielectrics are also compared to achieve an electro-thermal co-optimization of SOI-ATG LDMOS.