A low-power DCT IP core based on 2D algebraic integer encoding

Abstract

This paper discusses the application of a new two dimensional algebraic integer encoding scheme for the design of a DCT processor core for JPEG and MPEG applications. The paper concentrates on the efficient implementation of a 2D algebraic integer encoding procedure. The processor takes advantage of the low complexity, multiplierless, high-precision nature of the algebraic integer encoding scheme to achieve low power consumption. Test results from a proof-of-concept 0.18 /spl mu/m CMOS 8/spl times/8 DCT chip demonstrate a low power dissipation of 7.5 mW at 75 MHz.