An Efficient Refresh Strategy of Flash Memory via High Delay Blocks in LDPC

Abstract

With the development of flash memory, its storage density is gradually increased. A single flash memory cell can store more bits. But this makes it much less reliability. LDPC (i.e., Low Density Parity Check Code) has powerful error correction ability, which can help flash to solve this problem. However, there is a key problem with LDPC as an error-correcting code. It will make flash storage devices with low reliability suffer from high error correction delay. In this case, flash storage devices have greatly increased read latency, which affects device performance. In this work, we define high latency blocks according to LDPC latency of blocks, and propose a self-adaptive refresh scheme to reduce the read latency of flash storage devices. The basic idea is to refresh high latency blocks whenever it is detected to optimize read performance. In a periodic refresh mode, we test the performance of the refresh scheme in the case of wide workloads with different read and write ratios. The scheme reduces the average response time of flash storage devices by 6%-40% against baseline refresh schemes.