Depletion Width Modelling of Surrounded Channel Junctionless Field Effect Transistor

Abstract

A theoretical process of obtaining depletion width for surrounded channel Junction less field effect transistor is presented. Solution of 1-D Poisson’s equation under partial depletion leads to development of depletion width model. An analysis on how depletion width values varies with applied gate field, gate dielectric thickness, gate dielectric materials and channel position is also performed.