Pub Date : 2020-07-01DOI: 10.1109/ComPE49325.2020.9200152
Tamen Thapa Sarkar, L. Dewan, C. Mahanta
The control of inverted pendulum is a typical case as it exhibits a highly non-linear and unsteady phenomenon. This paper focusses on the comparative performance analysis for the swing up and stabilization of the inverted pendulum system. It uses trial and error method of LQR controller, algebraic approach for the selection of weighted matrices of the LQR controller, as well as the design and implementation of the state feedback pole-placement controller. The controllers used are for stabilization control and revolving up of Quanser based inverted pendulum system (QNET), which is rotary in the LabVIEW environment. The real-time operation has been carried out using the NI-ELVIS trainer kit, Quanser Rotary inverted pendulum system, and LabVIEW software.
{"title":"Real Time Swing up and Stabilization of Rotary Inverted Pendulum System","authors":"Tamen Thapa Sarkar, L. Dewan, C. Mahanta","doi":"10.1109/ComPE49325.2020.9200152","DOIUrl":"https://doi.org/10.1109/ComPE49325.2020.9200152","url":null,"abstract":"The control of inverted pendulum is a typical case as it exhibits a highly non-linear and unsteady phenomenon. This paper focusses on the comparative performance analysis for the swing up and stabilization of the inverted pendulum system. It uses trial and error method of LQR controller, algebraic approach for the selection of weighted matrices of the LQR controller, as well as the design and implementation of the state feedback pole-placement controller. The controllers used are for stabilization control and revolving up of Quanser based inverted pendulum system (QNET), which is rotary in the LabVIEW environment. The real-time operation has been carried out using the NI-ELVIS trainer kit, Quanser Rotary inverted pendulum system, and LabVIEW software.","PeriodicalId":6804,"journal":{"name":"2020 International Conference on Computational Performance Evaluation (ComPE)","volume":"12 1","pages":"517-522"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74903570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-07-01DOI: 10.1109/ComPE49325.2020.9200055
A. Bhattacharjee, S. Pradhan
Transistor aging affects has become a serious reliability issue in today’s deep submicron technology. With continuous scaling of transistor size along with process variation negative-bias temperature instability (NBTI) nowadays has become a serious reliability concern in analog and mixed-circuits. Due to NBTI induced increase in threshold voltage, analog circuit undergoes heavy performance degradation; as a result, their lifetime reduces. Op-amp is the basic building block of the Analog circuit. In earlier works, it has been observed that NBTI degradation is considerable when the op-amp circuit is used as a comparator. Also some circuits like buffer, current-steering DAC are affected due to aging. In this work, we have analyzed the aging effect on these circuits. We have also proposed a technique that mitigates NBTI degradation and increases the lifetime of the comparator. This technique increases the lifetime of comparator up to 4 years with negligible power overhead. This technique can be applied to other analog circuits also, which are affected due to NBTI. The simulation is done using cadence relxpert in UMC 28nm technology.
{"title":"Impact of Transistor Aging on the Reliability of the Analog Circuit","authors":"A. Bhattacharjee, S. Pradhan","doi":"10.1109/ComPE49325.2020.9200055","DOIUrl":"https://doi.org/10.1109/ComPE49325.2020.9200055","url":null,"abstract":"Transistor aging affects has become a serious reliability issue in today’s deep submicron technology. With continuous scaling of transistor size along with process variation negative-bias temperature instability (NBTI) nowadays has become a serious reliability concern in analog and mixed-circuits. Due to NBTI induced increase in threshold voltage, analog circuit undergoes heavy performance degradation; as a result, their lifetime reduces. Op-amp is the basic building block of the Analog circuit. In earlier works, it has been observed that NBTI degradation is considerable when the op-amp circuit is used as a comparator. Also some circuits like buffer, current-steering DAC are affected due to aging. In this work, we have analyzed the aging effect on these circuits. We have also proposed a technique that mitigates NBTI degradation and increases the lifetime of the comparator. This technique increases the lifetime of comparator up to 4 years with negligible power overhead. This technique can be applied to other analog circuits also, which are affected due to NBTI. The simulation is done using cadence relxpert in UMC 28nm technology.","PeriodicalId":6804,"journal":{"name":"2020 International Conference on Computational Performance Evaluation (ComPE)","volume":"52 1","pages":"212-216"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73019950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this report, the possibility of carryout All-Optical Logic (AOL) OR/AND logic gates are theoretically investigated using the concept of conversion of polarized light in single-waveguide coupled ring resonator. Numerical simulation outcomes confirm the planned model. The response time for polarization state conversion is as low as 0.2 ps. The Q-factor and some other factors like ‘figure of merits’ are also calculated to verify its utility. This may be used to describe other AOL circuits. The refractive index contrast, choice in source and pump power and wavelength together with appropriate height and width of the waveguide are adjusted to obtain switching activity.
{"title":"Design of All-Optical OR/AND Logic Gates using Conversion of Polarization States in Single-Waveguide Coupled Ring-Resonator","authors":"Madan Pal Singh, Jayanta Kumar Rakshit, Uttara Biswas, Gaurav Kumar Bharti, Aayushi Tiwari","doi":"10.1109/ComPE49325.2020.9200158","DOIUrl":"https://doi.org/10.1109/ComPE49325.2020.9200158","url":null,"abstract":"In this report, the possibility of carryout All-Optical Logic (AOL) OR/AND logic gates are theoretically investigated using the concept of conversion of polarized light in single-waveguide coupled ring resonator. Numerical simulation outcomes confirm the planned model. The response time for polarization state conversion is as low as 0.2 ps. The Q-factor and some other factors like ‘figure of merits’ are also calculated to verify its utility. This may be used to describe other AOL circuits. The refractive index contrast, choice in source and pump power and wavelength together with appropriate height and width of the waveguide are adjusted to obtain switching activity.","PeriodicalId":6804,"journal":{"name":"2020 International Conference on Computational Performance Evaluation (ComPE)","volume":"139 1","pages":"392-395"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73269201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-07-01DOI: 10.1109/ComPE49325.2020.9200016
S. Mathew, N. Nithin, R. Rao
This work analyses the influence of dielectric constant of spacer on the electrical characteristics as well as on two vital short channel effect parameters i.e DIBL and Subthreshold Swing of Dual Material Gate Junctionless FinFET (DMG-JLFinFET). Various spacer materials each with different dielectric constant, were used for 3D TCAD simulations. It was observed that high κ spacers gave higher value of ON current. Increase in leakage current was also observed for high κ spacers at higher negative gate bias. Subthreshold Swing (SS) as well as Drain Induced Barrier Lowering (DIBL) had reduced extensively with the increase in dielectric constant of spacer.
{"title":"Investigations on the Effect of Spacer Dielectrics on the DC Characteristics of Dual Material Gate Junctionless FinFETs","authors":"S. Mathew, N. Nithin, R. Rao","doi":"10.1109/ComPE49325.2020.9200016","DOIUrl":"https://doi.org/10.1109/ComPE49325.2020.9200016","url":null,"abstract":"This work analyses the influence of dielectric constant of spacer on the electrical characteristics as well as on two vital short channel effect parameters i.e DIBL and Subthreshold Swing of Dual Material Gate Junctionless FinFET (DMG-JLFinFET). Various spacer materials each with different dielectric constant, were used for 3D TCAD simulations. It was observed that high κ spacers gave higher value of ON current. Increase in leakage current was also observed for high κ spacers at higher negative gate bias. Subthreshold Swing (SS) as well as Drain Induced Barrier Lowering (DIBL) had reduced extensively with the increase in dielectric constant of spacer.","PeriodicalId":6804,"journal":{"name":"2020 International Conference on Computational Performance Evaluation (ComPE)","volume":"3 1","pages":"359-361"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73707549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-07-01DOI: 10.1109/ComPE49325.2020.9200113
Angshumala Talukdar, Kaushik Chandra Deva Sarma
One of the most important parameter of a device is electrostatic potential. A fully analytical potential model shown the distribution of electrostatic potential in a Normally on Double gate Junctionless field effect transistor is presented. In a normally on device work function of gate is lower than that of channel. A negative gate potential is applied to create a depletion layer underneath the gate region to turn the device on. The potential expression is derived from solution of Poisson's equation while considering that flat band voltage is zero. The potential expression in the channel region and source-drain regions are obtained separately. The validation of the model obtained is done with comparison to simulation results obtained from Cogenda VisualTCAD 2-D device simulator. The results obtained from the analytical potential model closely matches with TCAD simulation results. As the model is fully analytical in nature it helps in reducing the computational time.
{"title":"An Analytical Potential Model for Normally on Double Gate Junctionless Field Effect Transistor","authors":"Angshumala Talukdar, Kaushik Chandra Deva Sarma","doi":"10.1109/ComPE49325.2020.9200113","DOIUrl":"https://doi.org/10.1109/ComPE49325.2020.9200113","url":null,"abstract":"One of the most important parameter of a device is electrostatic potential. A fully analytical potential model shown the distribution of electrostatic potential in a Normally on Double gate Junctionless field effect transistor is presented. In a normally on device work function of gate is lower than that of channel. A negative gate potential is applied to create a depletion layer underneath the gate region to turn the device on. The potential expression is derived from solution of Poisson's equation while considering that flat band voltage is zero. The potential expression in the channel region and source-drain regions are obtained separately. The validation of the model obtained is done with comparison to simulation results obtained from Cogenda VisualTCAD 2-D device simulator. The results obtained from the analytical potential model closely matches with TCAD simulation results. As the model is fully analytical in nature it helps in reducing the computational time.","PeriodicalId":6804,"journal":{"name":"2020 International Conference on Computational Performance Evaluation (ComPE)","volume":"355 1","pages":"464-468"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73962084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-07-01DOI: 10.1109/ComPE49325.2020.9200147
Anjanmani Baro, Kaushik Chandra Deva Sarma
A simulation study on electrical characteristics of a Double gate Junctionless field effect transistor (JLFET) with triangle shaped spacer is reported. The structure consists of a spacer of the shape of a triangle extended upto the source and drain ohmic contacts. A simulation study on electrical performance has been done in COGENDA VisualTCAD 2-D Device Simulator 1.8.2 platform. The study shows that the use of spacer in triangle shape enhances Ion/Ioff ratio and subthreshold slope compared to a conventional JLFET.
{"title":"Study on Electrical Characteristics of Double gate Junctionless Field Effect Transistor With Triangle Shaped Spacer","authors":"Anjanmani Baro, Kaushik Chandra Deva Sarma","doi":"10.1109/ComPE49325.2020.9200147","DOIUrl":"https://doi.org/10.1109/ComPE49325.2020.9200147","url":null,"abstract":"A simulation study on electrical characteristics of a Double gate Junctionless field effect transistor (JLFET) with triangle shaped spacer is reported. The structure consists of a spacer of the shape of a triangle extended upto the source and drain ohmic contacts. A simulation study on electrical performance has been done in COGENDA VisualTCAD 2-D Device Simulator 1.8.2 platform. The study shows that the use of spacer in triangle shape enhances Ion/Ioff ratio and subthreshold slope compared to a conventional JLFET.","PeriodicalId":6804,"journal":{"name":"2020 International Conference on Computational Performance Evaluation (ComPE)","volume":"143 1","pages":"601-603"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80287937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-07-01DOI: 10.1109/ComPE49325.2020.9200091
Nikhil Tiwari, A. Singh
In an agricultural country like India, the success or failure of the harvest is highly dependent on the rainfall pattern of the country. India’s agriculture production is highly dependent on its precipitation behavior of the monsoon rainfall. Monsoon is the main source of water in India. Average rainfall prediction is a prime important factor for crop planning. Many of the studies have shown the direct influence of rainwater on the crops. This research has conducted a study on rainfall pattern in Indian states using machine learning techniques and algorithms, which utilizes government provided rainfall data from 1901-2017. This research proposes a study and analysis of rainfall in the Indian states using machine learning algorithms and compared their performances to the standard results.
{"title":"A Novel Study of Rainfall in the Indian States and Predictive Analysis using Machine Learning Algorithms","authors":"Nikhil Tiwari, A. Singh","doi":"10.1109/ComPE49325.2020.9200091","DOIUrl":"https://doi.org/10.1109/ComPE49325.2020.9200091","url":null,"abstract":"In an agricultural country like India, the success or failure of the harvest is highly dependent on the rainfall pattern of the country. India’s agriculture production is highly dependent on its precipitation behavior of the monsoon rainfall. Monsoon is the main source of water in India. Average rainfall prediction is a prime important factor for crop planning. Many of the studies have shown the direct influence of rainwater on the crops. This research has conducted a study on rainfall pattern in Indian states using machine learning techniques and algorithms, which utilizes government provided rainfall data from 1901-2017. This research proposes a study and analysis of rainfall in the Indian states using machine learning algorithms and compared their performances to the standard results.","PeriodicalId":6804,"journal":{"name":"2020 International Conference on Computational Performance Evaluation (ComPE)","volume":"98 1","pages":"199-204"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80999884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a Distance Function Modified Bug (DFMB) Algorithm with a random clockwise or anti-clockwise movement has been presented; offering optimum path length and less run time; which can be used for unmanned vehicle path tracking. Percent deviation in the run time of the algorithm has been compared with the other existing algorithms. In a static 2D environment where an obstacle is present; the traditional Bug approach is to first seek the shortest path from start to goal location and follow that path. If the path passes through any obstacle, then it starts wall following behaviour to find the shortest way to the goal. In our approach, we have introduced an improved distance calculation method with some newly developed parameters. The DFMB algorithm offers a smooth trajectory from source to goal location with obstacle avoidance in a given 2D environment without blindly following the boundary of the obstacle. Various simulation results and suitable comparative analysis have been presented to prove the superiority of the algorithm. We have done the effective realization of the algorithm, using MATLAB.
{"title":"Computational Study of DFMB Algorithm for Unmanned Vehicle in Static 2D Environment","authors":"Subhradip Mukherjee, Rajagopal Kumar, Siddhanta Borah","doi":"10.1109/ComPE49325.2020.9200179","DOIUrl":"https://doi.org/10.1109/ComPE49325.2020.9200179","url":null,"abstract":"In this paper, a Distance Function Modified Bug (DFMB) Algorithm with a random clockwise or anti-clockwise movement has been presented; offering optimum path length and less run time; which can be used for unmanned vehicle path tracking. Percent deviation in the run time of the algorithm has been compared with the other existing algorithms. In a static 2D environment where an obstacle is present; the traditional Bug approach is to first seek the shortest path from start to goal location and follow that path. If the path passes through any obstacle, then it starts wall following behaviour to find the shortest way to the goal. In our approach, we have introduced an improved distance calculation method with some newly developed parameters. The DFMB algorithm offers a smooth trajectory from source to goal location with obstacle avoidance in a given 2D environment without blindly following the boundary of the obstacle. Various simulation results and suitable comparative analysis have been presented to prove the superiority of the algorithm. We have done the effective realization of the algorithm, using MATLAB.","PeriodicalId":6804,"journal":{"name":"2020 International Conference on Computational Performance Evaluation (ComPE)","volume":"23 1","pages":"126-131"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85520140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-07-01DOI: 10.1109/ComPE49325.2020.9200030
J. Patni, Souradeep Banerjee, Devyanshi Tiwari
As the scale of cloud infrastructure is augmenting, so is the number of instances that needs to be provisioned. As a result, there is a requirement for automating the process of managing infrastructure instances to facilitate development, staging, and production environments. The purpose of this paper is to understand ‘Infrastructure as a code’ (IaC) in relation to Software Defined Infrastructure. Using Azure Resource Manager (ARM) Templates we will demonstrate the benefit and importance of IaC by deploying a web application on Microsoft Azure using only code. The use of ARM templates was found to increase the agility of the deployment and management process. We will also demonstrate IaC using Terraform and Pulumi. The paper also discusses the correlation of IaC with the concept of code reusability and repeatability.
{"title":"Infrastructure as a Code (IaC) to Software Defined Infrastructure using Azure Resource Manager (ARM)","authors":"J. Patni, Souradeep Banerjee, Devyanshi Tiwari","doi":"10.1109/ComPE49325.2020.9200030","DOIUrl":"https://doi.org/10.1109/ComPE49325.2020.9200030","url":null,"abstract":"As the scale of cloud infrastructure is augmenting, so is the number of instances that needs to be provisioned. As a result, there is a requirement for automating the process of managing infrastructure instances to facilitate development, staging, and production environments. The purpose of this paper is to understand ‘Infrastructure as a code’ (IaC) in relation to Software Defined Infrastructure. Using Azure Resource Manager (ARM) Templates we will demonstrate the benefit and importance of IaC by deploying a web application on Microsoft Azure using only code. The use of ARM templates was found to increase the agility of the deployment and management process. We will also demonstrate IaC using Terraform and Pulumi. The paper also discusses the correlation of IaC with the concept of code reusability and repeatability.","PeriodicalId":6804,"journal":{"name":"2020 International Conference on Computational Performance Evaluation (ComPE)","volume":"164 1","pages":"575-578"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86380050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-07-01DOI: 10.1109/ComPE49325.2020.9200170
Vishwanath G. Garagad, N. Iyer, Heera G Wali
Internet of Things (IoT), is emerging as the most evolving technology and contributing to the critical domain areas from transportation, to manufacturing, to energy, to automation, to space, to defence, to health care. IoT system architecture is an aggregation of Cyber-Physical Systems (CPS) that include multiple edge nodes like sensors, actuators or devices as primary components of the system. The crucial element in the existence and evolution of IoT is collecting rich and diverse data stream from the application of interest. Information extracted from data inference mostly drives the decisional policies of the cyber-physical system, which govern the functionality of critical application areas. Edge devices play the role of data generator, collector, or integrator of the system. The fact that these edge devices are ubiquitous and placed in easily accessible unsecured locations make then prone to cyber-attacks. The data sourced through these systems being safety-critical and high commercial value, draw the attention of adversary to attempt for cyber attacks unceasingly. This survey paper contributes in terms of identifying the security threats and challenges related to privacy and security of data in the context of IoT systems and CPS. Data tampering and malicious infusion are the prime sources of threats. The paper also outlines the current state of art research to identify and mitigate such data integrity threats and attacks.
{"title":"Data Integrity: A security threat for Internet of Things and Cyber-Physical Systems","authors":"Vishwanath G. Garagad, N. Iyer, Heera G Wali","doi":"10.1109/ComPE49325.2020.9200170","DOIUrl":"https://doi.org/10.1109/ComPE49325.2020.9200170","url":null,"abstract":"Internet of Things (IoT), is emerging as the most evolving technology and contributing to the critical domain areas from transportation, to manufacturing, to energy, to automation, to space, to defence, to health care. IoT system architecture is an aggregation of Cyber-Physical Systems (CPS) that include multiple edge nodes like sensors, actuators or devices as primary components of the system. The crucial element in the existence and evolution of IoT is collecting rich and diverse data stream from the application of interest. Information extracted from data inference mostly drives the decisional policies of the cyber-physical system, which govern the functionality of critical application areas. Edge devices play the role of data generator, collector, or integrator of the system. The fact that these edge devices are ubiquitous and placed in easily accessible unsecured locations make then prone to cyber-attacks. The data sourced through these systems being safety-critical and high commercial value, draw the attention of adversary to attempt for cyber attacks unceasingly. This survey paper contributes in terms of identifying the security threats and challenges related to privacy and security of data in the context of IoT systems and CPS. Data tampering and malicious infusion are the prime sources of threats. The paper also outlines the current state of art research to identify and mitigate such data integrity threats and attacks.","PeriodicalId":6804,"journal":{"name":"2020 International Conference on Computational Performance Evaluation (ComPE)","volume":"82 3","pages":"244-249"},"PeriodicalIF":0.0,"publicationDate":"2020-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91454075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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