A Novel Method for Air-Gap Formation around Via-Middle (VM) TSVs for Effective Reduction in Keep-Out Zones (KOZ)

Abstract

Significant stress is induced in the crystalline Si area around a Cu-filled Through Silicon Via (TSV) due to the large mismatch in the co-efficient of thermal expansion (CTE) between Si and Cu. As a result, CMOS devices fabricated within the stressed Si region will show undesired variations in their electrical performance. This paper reports a novel method to isolate the TSV-induced stress from active CMOS devices through the formation of embedded air-gaps. As the air-gaps are embedded in the Si, stress isolation can be done without compromising on the usable Si area. Formation of the air-gaps have been demonstrated experimentally using a high temperature anneal in a de-oxidizing ambient. Stress reduction in the Si lattice, in the presence of the embedded air-gaps, will be studied through thermo-mechanical stress simulation. Effect of the impact of air-gap design will also be discussed.