The components of Integrated Circuit (IC) devices are susceptible to moisture absorption at different stages of the production environment which can lead to hygrothermal stresses during the surface mounting process. The moisture concentration in electronic packages can be determined based on the wetness approach. If the saturated concentration value is dependent on temperature or time, the analogy between the wetness equation and the standard diffusion equation is not valid and requires special treatment. In this study, an alternative formulation, peridynamics, is utilized for the solution of wetness field equation in the case of saturated concentration varying with time. The formulation is implemented in the commercial finite element software, ANSYS, by utilizing traditional finite elements and solvers to make the computations more efficient. The peridynamic wetness approach is validated by considering various problem cases for absorption and desorption with multi-material systems representative of electronic packages.
{"title":"Peridynamic Solution of Wetness Equation with Time Dependent Saturated Concentration in ANSYS Framework","authors":"C. Diyaroglu, E. Madenci, S. Oterkus, E. Oterkus","doi":"10.1109/ECTC.2017.297","DOIUrl":"https://doi.org/10.1109/ECTC.2017.297","url":null,"abstract":"The components of Integrated Circuit (IC) devices are susceptible to moisture absorption at different stages of the production environment which can lead to hygrothermal stresses during the surface mounting process. The moisture concentration in electronic packages can be determined based on the wetness approach. If the saturated concentration value is dependent on temperature or time, the analogy between the wetness equation and the standard diffusion equation is not valid and requires special treatment. In this study, an alternative formulation, peridynamics, is utilized for the solution of wetness field equation in the case of saturated concentration varying with time. The formulation is implemented in the commercial finite element software, ANSYS, by utilizing traditional finite elements and solvers to make the computations more efficient. The peridynamic wetness approach is validated by considering various problem cases for absorption and desorption with multi-material systems representative of electronic packages.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"42 1","pages":"1014-1019"},"PeriodicalIF":0.0,"publicationDate":"2017-08-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76271320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chenhui Li, B. Smalbrugge, Teng Li, R. Stabile, O. Raz
In this paper, we propose a novel way for 3D packaging of optical and electrical dies for parallel optical interconnections based on wet etched silicon interposer. The process flow of silicon interposer fabrication is demonstrated. Through three steps of deeply wet etching of silicon, a multi-level cavity is formed for embedding and flip-chipping of optical die and electrical die, and the optical through silicon vias for optical I/Os are opened. After flip chip bonding, a designed 50 µm air gap is formed between electronics and optics for thermal isolation. The heat transfer is also simulated to validate the thermal isolation air gap between dies. After fabricating, a 10 Gbps 12-channel receiver is assembled on the silicon interposer, and the sub-module is scaled down to 4 mm by 6 mm. The performance of the fully assembled sub-module is tested on a probe station. Clear eye patterns are captured for each channel. Bit error rate (BER) testing is also performed showing uniform BER with performance matching that of commercial MM receiver.
{"title":"3D Packaging of Embedded Opto-Electronic Die and CMOS IC Based on Wet Etched Silicon Interposer","authors":"Chenhui Li, B. Smalbrugge, Teng Li, R. Stabile, O. Raz","doi":"10.1109/ECTC.2017.222","DOIUrl":"https://doi.org/10.1109/ECTC.2017.222","url":null,"abstract":"In this paper, we propose a novel way for 3D packaging of optical and electrical dies for parallel optical interconnections based on wet etched silicon interposer. The process flow of silicon interposer fabrication is demonstrated. Through three steps of deeply wet etching of silicon, a multi-level cavity is formed for embedding and flip-chipping of optical die and electrical die, and the optical through silicon vias for optical I/Os are opened. After flip chip bonding, a designed 50 µm air gap is formed between electronics and optics for thermal isolation. The heat transfer is also simulated to validate the thermal isolation air gap between dies. After fabricating, a 10 Gbps 12-channel receiver is assembled on the silicon interposer, and the sub-module is scaled down to 4 mm by 6 mm. The performance of the fully assembled sub-module is tested on a probe station. Clear eye patterns are captured for each channel. Bit error rate (BER) testing is also performed showing uniform BER with performance matching that of commercial MM receiver.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"62 1","pages":"551-556"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80746851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we demonstrate that low insertion loss is achieved in channel-shuffling polymer waveguide having graded-index (GI) square cores (24 channels × 24 channels) with a 125-mm interchannel pitch. Although there are several fabrication methods for GI-core polymer optical waveguides proposed, the index profiles formed in the square cores are not ideally symmetric, when conventional photo-lithography method is applied. Hence, we apply the imprint method for the GI square core polymer waveguides with ideally symmetric index profile. First, we design the structure of channel-shuffling waveguide to exhibit low insertion loss, and then experimentally fabricate the waveguide.
{"title":"Low Loss Channel-Shuffling Polymer Waveguides: Design and Fabrication","authors":"Kohei Abe, Yutaro Oizumi, Y. Taira, T. Ishigure","doi":"10.1109/ECTC.2017.223","DOIUrl":"https://doi.org/10.1109/ECTC.2017.223","url":null,"abstract":"In this paper, we demonstrate that low insertion loss is achieved in channel-shuffling polymer waveguide having graded-index (GI) square cores (24 channels × 24 channels) with a 125-mm interchannel pitch. Although there are several fabrication methods for GI-core polymer optical waveguides proposed, the index profiles formed in the square cores are not ideally symmetric, when conventional photo-lithography method is applied. Hence, we apply the imprint method for the GI square core polymer waveguides with ideally symmetric index profile. First, we design the structure of channel-shuffling waveguide to exhibit low insertion loss, and then experimentally fabricate the waveguide.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"400 1","pages":"526-531"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76461043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Iwanabe, Kenichi Nakadozono, M. Sakamoto, T. Asano
Dynamic changes in distribution of mechanical strain generated during wire bonding in Si under and near the bonding pad were measured by using a piezoresistive linear array sensor. The sensor was designed to be able to determine strains in the directions normal and parallel to the surface. Bonding dynamics of Cu and Au balls were investigated. We can clearly observe the oscillating strain according to the application of 150 kHz ultrasonic vibration. It was also clearly observed that the position of the largest compressive strain moved from the center of the ball to the periphery according to the progress of bonding under the application of the ultrasonic vibration. Bonding of Cu was found to generate larger strain than bonding of Au. A large oscillating tensile strain generated at the periphery of Cu ball when ultrasonic amplitude is increased is found to cause fracture of Si. The largest residual strain is observed for Cu bonding at the location where the end of capillary tool was present during bonding.
{"title":"Dynamic Strain of Ultrasonic Cu and Au Ball Bonding Measured In-Situ by Using Silicon Piezoresistive Sensor","authors":"K. Iwanabe, Kenichi Nakadozono, M. Sakamoto, T. Asano","doi":"10.1109/ECTC.2017.316","DOIUrl":"https://doi.org/10.1109/ECTC.2017.316","url":null,"abstract":"Dynamic changes in distribution of mechanical strain generated during wire bonding in Si under and near the bonding pad were measured by using a piezoresistive linear array sensor. The sensor was designed to be able to determine strains in the directions normal and parallel to the surface. Bonding dynamics of Cu and Au balls were investigated. We can clearly observe the oscillating strain according to the application of 150 kHz ultrasonic vibration. It was also clearly observed that the position of the largest compressive strain moved from the center of the ball to the periphery according to the progress of bonding under the application of the ultrasonic vibration. Bonding of Cu was found to generate larger strain than bonding of Au. A large oscillating tensile strain generated at the periphery of Cu ball when ultrasonic amplitude is increased is found to cause fracture of Si. The largest residual strain is observed for Cu bonding at the location where the end of capillary tool was present during bonding.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"47 1","pages":"1786-1792"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90912710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Ishigure, K. Katori, Hoshihiko Toda, Kazuki Yasuhara
In this paper, we present axially tapered circular core polymer optical waveguides which allow high-efficiency light coupling between optical components such as light sources, fibers/waveguides, and detectors with a wide misalignment tolerance. We experimentally fabricate the taper shaped polymer waveguides by applying imprinting method or the Mosquito method, and both experimentally and theoretically verify the high optical functionality of the tapered waveguides from the optical packaging technology point of view.
{"title":"Axially Tapered Circular Core Polymer Optical Waveguides Enabling Highly Efficient Light Coupling","authors":"T. Ishigure, K. Katori, Hoshihiko Toda, Kazuki Yasuhara","doi":"10.1109/ECTC.2017.214","DOIUrl":"https://doi.org/10.1109/ECTC.2017.214","url":null,"abstract":"In this paper, we present axially tapered circular core polymer optical waveguides which allow high-efficiency light coupling between optical components such as light sources, fibers/waveguides, and detectors with a wide misalignment tolerance. We experimentally fabricate the taper shaped polymer waveguides by applying imprinting method or the Mosquito method, and both experimentally and theoretically verify the high optical functionality of the tapered waveguides from the optical packaging technology point of view.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"40 1","pages":"1600-1605"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74083566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Tatsumi, M. Inagaki, K. Kamei, T. Iizuka, Hiroaki Narimatsu, Nobuaki Sato, K. Shimizu, Kazutoshi Ueda, Akihiro Imakire, M. Hikita, Rikiya Kamimura, K. Sugiura, K. Tsuruta, Keiji Toda
Aiming for application to the inverter system of HEV and EV, we have developed a novel packaging technique for SiC power devices based on Nickel Micro Plating Bonding (NMPB) technique. We implemented heat resistant mounting of SiC schottky barrier diode (SBD) on the TO247 type package and confirmed the rectifying behavior even after the high temperature storage for 500hr at 250°C without any significant degradations. We also fabricated one-leg inverter modules mounting SBDs and MOSFETs using newly designed lead frames for NMPB process. The module showed normal rectifying and switching behavior even at high temperature such as about 250°C.
{"title":"Development of Packaging Technology for High Temperature Resistant SiC Module of Automobile Application","authors":"K. Tatsumi, M. Inagaki, K. Kamei, T. Iizuka, Hiroaki Narimatsu, Nobuaki Sato, K. Shimizu, Kazutoshi Ueda, Akihiro Imakire, M. Hikita, Rikiya Kamimura, K. Sugiura, K. Tsuruta, Keiji Toda","doi":"10.1109/ECTC.2017.103","DOIUrl":"https://doi.org/10.1109/ECTC.2017.103","url":null,"abstract":"Aiming for application to the inverter system of HEV and EV, we have developed a novel packaging technique for SiC power devices based on Nickel Micro Plating Bonding (NMPB) technique. We implemented heat resistant mounting of SiC schottky barrier diode (SBD) on the TO247 type package and confirmed the rectifying behavior even after the high temperature storage for 500hr at 250°C without any significant degradations. We also fabricated one-leg inverter modules mounting SBDs and MOSFETs using newly designed lead frames for NMPB process. The module showed normal rectifying and switching behavior even at high temperature such as about 250°C.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"184 1","pages":"1316-1321"},"PeriodicalIF":0.0,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80515281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Bajwa, SivaChandra Jangam, Saptadeep Pal, N. Marathe, T. Bai, T. Fukushima, M. Goorsky, S. Iyer
The scaling of package and circuit board dimensions is central to heterogeneous system integration. We describe our solderless direct metal-to-metal low pressure ( 20 MPa. The combined reduction of dielet interconnect pitch, dielet-to-dielet spacing and trace pitch will enable a Moore's law for packaging.
{"title":"Heterogeneous Integration at Fine Pitch (≤ 10 µm) Using Thermal Compression Bonding","authors":"A. Bajwa, SivaChandra Jangam, Saptadeep Pal, N. Marathe, T. Bai, T. Fukushima, M. Goorsky, S. Iyer","doi":"10.1109/ECTC.2017.240","DOIUrl":"https://doi.org/10.1109/ECTC.2017.240","url":null,"abstract":"The scaling of package and circuit board dimensions is central to heterogeneous system integration. We describe our solderless direct metal-to-metal low pressure ( 20 MPa. The combined reduction of dielet interconnect pitch, dielet-to-dielet spacing and trace pitch will enable a Moore's law for packaging.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"6 1","pages":"1276-1284"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84760604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Teng Li, S. Dorrestein, G. Guelbenzu, Chenhui Li, R. Stabile, O. Raz
High bandwidth density on-board optical transmitter is reported in this paper. This on-board transmitter contains 4×12-channel 10Gbps CMOS driver ICs and 4×12-channel 850nm Multimode (MM) VCSEL arrays, with a total 48×10Gbps bandwidth and is packaged through flip-chip bonding on a flexible printed circuit (FPC) with SnAg solder bumps. Due to the compact package design, based on a commercial 1mm pitch ISI HoLi pin grid array (PGA) connector, the size of FPC is only 31.5mm × 31.5mm and it offers a state-of-art bandwidth density of 0.483Gbps/mm2. Investigation of RF signal propagation on the FPC is carried out for design validation at 10Gbps and to further explore the potential of the suggested platform differential pairs are simulated up to 30Gbps. An optical straight lens connector is used to couple the light to a single 48 fibers MT connector. To validate the design concept the fully assembled transmitter is tested at 10Gbps. Bit error rates for all 48 channels at 10Gbps as well as eye diagrams for few representative channels are reported.
{"title":"48×10 Gbps Cost-Effective FPC-Based On-Board Optical Transmitter with PGA Connector","authors":"Teng Li, S. Dorrestein, G. Guelbenzu, Chenhui Li, R. Stabile, O. Raz","doi":"10.1109/ECTC.2017.224","DOIUrl":"https://doi.org/10.1109/ECTC.2017.224","url":null,"abstract":"High bandwidth density on-board optical transmitter is reported in this paper. This on-board transmitter contains 4×12-channel 10Gbps CMOS driver ICs and 4×12-channel 850nm Multimode (MM) VCSEL arrays, with a total 48×10Gbps bandwidth and is packaged through flip-chip bonding on a flexible printed circuit (FPC) with SnAg solder bumps. Due to the compact package design, based on a commercial 1mm pitch ISI HoLi pin grid array (PGA) connector, the size of FPC is only 31.5mm × 31.5mm and it offers a state-of-art bandwidth density of 0.483Gbps/mm2. Investigation of RF signal propagation on the FPC is carried out for design validation at 10Gbps and to further explore the potential of the suggested platform differential pairs are simulated up to 30Gbps. An optical straight lens connector is used to couple the light to a single 48 fibers MT connector. To validate the design concept the fully assembled transmitter is tested at 10Gbps. Bit error rates for all 48 channels at 10Gbps as well as eye diagrams for few representative channels are reported.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"35 1","pages":"1755-1760"},"PeriodicalIF":0.0,"publicationDate":"2017-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80771722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chunmei Wang, K. Chui, Xiangy-Yu Wang, T. Lim, Mingbin Yu, Gilbert See, G. Yu
This paper presents the demonstration of integrated passive devices on a 300mm mold-first FOWLP technology platform with 3 metal layers (Cu RDL) build-up. In this case, a low-temperature cure, negative-tone polyimide (PI) material is selected as the inter-layer dielectric. MIM capacitors were fabricated on top of M1 RDL layer with low temperature CVD deposited inorganic as the dielectric and typical RDL barrier metal as the top and bottom electrode. Resistors were formed after M1 RDL layer by using typical RDL barrier metal as the thin film resistor. Last but not least, inductors were built on M2 RDL layer over epoxy mold material. Test keys for MIM capacitors, resistors and inductors were designed for electrical and RF characterization at the M2 layer.
{"title":"Passive Devices Fabrication on FOWLP and Characterization for RF Applications","authors":"Chunmei Wang, K. Chui, Xiangy-Yu Wang, T. Lim, Mingbin Yu, Gilbert See, G. Yu","doi":"10.1109/ECTC.2017.315","DOIUrl":"https://doi.org/10.1109/ECTC.2017.315","url":null,"abstract":"This paper presents the demonstration of integrated passive devices on a 300mm mold-first FOWLP technology platform with 3 metal layers (Cu RDL) build-up. In this case, a low-temperature cure, negative-tone polyimide (PI) material is selected as the inter-layer dielectric. MIM capacitors were fabricated on top of M1 RDL layer with low temperature CVD deposited inorganic as the dielectric and typical RDL barrier metal as the top and bottom electrode. Resistors were formed after M1 RDL layer by using typical RDL barrier metal as the thin film resistor. Last but not least, inductors were built on M2 RDL layer over epoxy mold material. Test keys for MIM capacitors, resistors and inductors were designed for electrical and RF characterization at the M2 layer.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"54 1","pages":"312-318"},"PeriodicalIF":0.0,"publicationDate":"2017-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77850674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Muthukumaraswamy, K. Chui, W. Y. Lim, Jun Yu, Serine Soh, Leong Yew Wing, Huamao Lin, S. Wickramanayaka
This paper presents the design considerations for thin-film magnetic power inductors for integrated voltage regulator (IVR). Optimum design parameters for solenoid inductors are arrived at that maximize key performance metrics such as quality factor, inductor efficiency, inductance density, and operation frequency. A fabrication approach to integrate the solenoid inductor with thin-film magnetic material is presented. Finally, electrical characterization of a set of test inductors that were fabricated is carried out and the results such as inductance, quality factor, DC resistance are presented.
{"title":"Thin-Film Magnetic Inductor for Integrated Power Management","authors":"A. Muthukumaraswamy, K. Chui, W. Y. Lim, Jun Yu, Serine Soh, Leong Yew Wing, Huamao Lin, S. Wickramanayaka","doi":"10.1109/ECTC.2017.289","DOIUrl":"https://doi.org/10.1109/ECTC.2017.289","url":null,"abstract":"This paper presents the design considerations for thin-film magnetic power inductors for integrated voltage regulator (IVR). Optimum design parameters for solenoid inductors are arrived at that maximize key performance metrics such as quality factor, inductor efficiency, inductance density, and operation frequency. A fabrication approach to integrate the solenoid inductor with thin-film magnetic material is presented. Finally, electrical characterization of a set of test inductors that were fabricated is carried out and the results such as inductance, quality factor, DC resistance are presented.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"36 1","pages":"1485-1490"},"PeriodicalIF":0.0,"publicationDate":"2017-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85125480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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