A CMOS mixed-signal integrated circuit having a reduced vector set and closed-loop analog test architecture

Abstract

This paper describes a mixed-signal IC that employs a test architecture consisting of multiple selectable sub-scan chains (SSCs), which the authors have termed "pseudo full scan". This implementation reduces test pattern length and improves fault grading. An additional scan chain of boundary shift register latches (BSRLs) is used to sensitize the analog section of the IC to permit closed-loop testing. A mixed-signal IC using this architecture can be tested with a less expensive digital IC tester. Modeling for standard automatic test pattern generation (ATPG) tools is also presented.