VLSI implementation of a realtime wavelet video coder

Abstract

The architecture of a realtime wavelet video coder is described, with the main emphasis put on memory bandwidth reduction and efficient VLSI implementation. The proposed architecture adopts a modified 2-D subband decomposition scheme, alongside of a parallelized pipelined Embedded Zerotree Wavelet coder architecture. The video encoder is integrated in a 0.35 /spl mu/m 3LM chip by using 341 K transistors on a 4.93/spl times/4.93 mm/sup 2/ die, which can process 720/spl times/480 30 fps pictures in realtime.