Development of cost-effective wafer level process for 3D-integration with bump-less TSV interconnects

K. Fujimoto, N. Maeda, H. Kitada, Y. Kim, S. Kodama, T. Nakamura, K. Suzuki, T. Ohba
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引用次数: 2

Abstract

The multi-stack processes for wafer-on-wafer (WOW) have been developed. The key features are bumpless interconnects adapted to TSVs and extendibility for chip-on-wafer (COW) taking high throughput into account. In order to realize the multi-stacked wafers with ultra thinned wafer of less than 10μm with an adhesive polymer, several processes have been optimized. The thickness of the wafer after back-grinding was controlled within the total thickness variation (TTV) of 1.2μm on wafer-level of 8 inch. As the dielectric film for the side wall of though silicon vias (TSV), SiN film with low deposition temperature of 150 °C has been developed and applied for TSV process without degradation for electrical characteristics. The uniformity of Cu electro-plating has been improved that the overburdened Cu from the surface was decreased from 13.3 μm to 0.7 μm by optimizing plating solution. The CMP process following Cu electro-plating has been customized for the high rate of 5 μm/min. Finally, the stacked wafer has been evaluated for thermal cycle test (TCT) of 100 cycles with -65 to 150 °C. The result showed that there was no degradation for reliability and packaging process.
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开发具有成本效益的晶圆级3d集成工艺与无碰撞TSV互连
硅片对硅片(WOW)的多层叠工艺得到了发展。主要特点是适合tsv的无凹凸互连和考虑到高吞吐量的片上(COW)的可扩展性。为了实现小于10μm的超薄晶片与粘接聚合物的多层堆叠,对几种工艺进行了优化。反磨后的晶圆厚度在8英寸晶圆级上控制在总厚度变化(TTV) 1.2μm以内。作为透硅通孔(TSV)侧壁的介质膜,沉积温度低至150℃的SiN薄膜已被开发出来并应用于TSV工艺,且其电特性没有退化。通过对镀液的优化,Cu镀层的均匀性得到了改善,镀层表面的过量Cu从13.3 μm减小到0.7 μm。定制了铜电镀后的CMP工艺,速度可达5 μm/min。最后,对堆叠晶圆进行了-65至150°C的100次热循环测试(TCT)。结果表明,在可靠性和封装过程中没有退化。
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Parasitic electrical and electromagnetic effects Heat management Passive electronic components Interconnection technology Reliability and maintainability
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