A 0.9V, 3.1–10.6 GHz CMOS LNA with high gain and wideband input match in 90 nm CMOS process

S. Pandey, P. Kondekar, K. Nigam, D. Sharma
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引用次数: 4

Abstract

In this paper, a high gain and wideband input match CMOS low-noise amplifier (LNA) is presented for the ultra-wide band (UWB) application. The main novelty lies in significant improvement in bandwidth by using the inverter cell at the input node, with a peaking inductor at the gate of NMOS device. Self-forward-body-bias (SFBB) concept is also used within the inverter cell to mitigate the trade-off between input matching and power consumption. In the second stage, self bias resistive feedback circuit with the drain peaking inductor is used to increase the gain as well as output matching. Using a standard 90 nm CMOS process, the proposed LNA exhibits a peak gain of 15.3 dB at 9.4 GHz, while, it consumes 13.5 mW power from a 0.9 V supply voltage. The simulation results show S11 <−10 dB from 4.6–10.6 GHz frequency, minimum noise figure (NFmin) of 1.21–4.6 dB, output return loss −32 dB1 in the frequency range of 3.1–10.6 GHz. When a two tone test is performed with a frequency spacing of 10 MHz, a highest value of third order input intercept point (IIP3) of −3 dBm is achieved. Its other significant advantages are small group delay variation (±50 ps), and gain variation of ±1.21 dB.
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一个0.9V, 3.1-10.6 GHz的CMOS LNA,具有高增益和宽带输入匹配的90 nm CMOS工艺
本文提出了一种用于超宽带应用的高增益宽带输入匹配CMOS低噪声放大器。主要的新颖之处在于通过在输入节点使用逆变器单元,在NMOS器件的栅极处使用峰值电感器,显著提高了带宽。自正向体偏置(SFBB)概念也用于逆变器单元,以减轻输入匹配和功耗之间的权衡。在第二阶段,采用带漏极峰值电感的自偏置电阻反馈电路来提高增益和输出匹配。采用标准的90 nm CMOS工艺,该LNA在9.4 GHz时的峰值增益为15.3 dB,而在0.9 V电源电压下功耗为13.5 mW。仿真结果表明,S11在3.1 ~ 10.6 GHz的频率范围内。在频率间隔为10mhz的双音测试中,三阶输入截距(IIP3)的最大值为−3dbm。它的其他显著优点是群延迟变化小(±50 ps),增益变化为±1.21 dB。
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