An improved technique to increase noise-tolerance in dynamic digital circuits

Abstract

Due to the rapid scaling of the transistor and interconnect dimensions the VLSI circuit technology is having an impressive advancement. However, noise issues emerge as an important cost in deep submicron circuits. In this paper we propose an improved noise-tolerant dynamic digital circuit technique. By using a charge redistribution process together with the conventional precharge of internal nodes in logic gates, the noise immunity is increased. Simulation results show an improvement of up to 8.6/spl times/over conventional dynamic logic.