Low-frequency noise reduction technique for accelerometer readout circuit

Abstract

This paper proposed a random chopper (RC) architecture for use in a capacitive accelerometer readout circuit. This technique randomizes low-frequency flicker noise to be more thermal-noise-like, and also boosts the small signal charges due to acceleration. The noise-equivalent acceleration (NEA) of the proposed RC readout circuit is greatly reduced compared with conventional correlated double sampling (CDS) approaches. The proposed method also eliminates the long propagating path during the CDS subtraction phase. This benefits the operation speed and power consumption of the operational transconductance amplifier (OTA) design of the readout circuit. The HSPICE© transient noise simulation results shows that the proposed RC architecture can reach 75 μg/rtHz NEA while reducing the current consumption to 6 μA. This low-power and low-noise features make this RC accelerometer suitable for wearable applications.