Lan Peng, Soon-Wook Kim, F. Inoue, Teng Wang, A. Phommahaxay, P. Verdonck, A. Jourdain, J. de Vos, E. Sleeckx, H. Struyf, Andy Miller, G. Beyer, E. Beyne, Mike Soules, S. Lutter
{"title":"Development of multi-stack dielectric wafer bonding","authors":"Lan Peng, Soon-Wook Kim, F. Inoue, Teng Wang, A. Phommahaxay, P. Verdonck, A. Jourdain, J. de Vos, E. Sleeckx, H. Struyf, Andy Miller, G. Beyer, E. Beyne, Mike Soules, S. Lutter","doi":"10.1109/ICEPT.2016.7583082","DOIUrl":null,"url":null,"abstract":"We investigate multi-stack dielectric wafer bonding through two integration schemes, which provide different paths to realize vertical integration of multiple device layers. Key process steps are evaluated and optimized to enable void-less bonds at different bonding layers. Meanwhile, issues related to the wafer edge are discovered during the backside processing and the impact is analyzed. Finally, N=4 stacks are successfully demonstrated with high quality interfaces formed by dielectric bonding.","PeriodicalId":6881,"journal":{"name":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","volume":"1 1","pages":"22-25"},"PeriodicalIF":0.0000,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 17th International Conference on Electronic Packaging Technology (ICEPT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEPT.2016.7583082","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
We investigate multi-stack dielectric wafer bonding through two integration schemes, which provide different paths to realize vertical integration of multiple device layers. Key process steps are evaluated and optimized to enable void-less bonds at different bonding layers. Meanwhile, issues related to the wafer edge are discovered during the backside processing and the impact is analyzed. Finally, N=4 stacks are successfully demonstrated with high quality interfaces formed by dielectric bonding.
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