Orthogonal Signal Generation based PLL using Arbitrary Order Exact Differentiator with Inherent Disturbance Rejection for Single Phase Systems

Satyanarayana Muddasani, A. V. R. Teja
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Abstract

Use of Derivative based PLL is one of the simplest and fastest solution for phase-locked loops in single phase systems. The dynamics of Derivative-PLL are comparatively better than other methods, but it exhibits high frequency noise amplification and also under performs in non-ideal grid conditions. In this paper, a robust arbitrary order exact differentiator is proposed as a solution to generate noise free, fast and exact orthogonal signal by utilizing second order generalized differentiator method which is used further to formulate a PLL that is immune to high frequency noise and performs well under various disturbances in voltage, frequency, phase, harmonics, noise and DC-offset in grid voltage. The proposed PLL is modeled using MATLAB/SIMULINK and is tested for standard grid conditions. Typical results are reported and are compared with existing PLLs. It is found that the proposed method is not only simple and immune to noise and disturbances but also superior compared to other PLLs.
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基于任意阶精确微分器的正交信号生成锁相环,具有固有抗扰性
使用基于导数的锁相环是单相系统中锁相环最简单和最快的解决方案之一。导数锁相环的动力学性能相对较好,但存在高频噪声放大问题,在非理想网格条件下性能较差。本文提出了一种鲁棒任意阶精确微分器,作为利用二阶广义微分器方法产生无噪声、快速精确正交信号的解决方案,并进一步利用该方法设计出一种不受高频噪声影响的锁相环,该锁相环在电压、频率、相位、谐波、噪声和电网电压直流偏置等各种干扰下都有良好的性能。利用MATLAB/SIMULINK对所提出的锁相环进行了建模,并在标准网格条件下进行了测试。报告了典型结果,并与现有锁相环进行了比较。结果表明,该方法不仅简单,而且不受噪声和干扰的影响,而且与其他锁相环相比具有优越性。
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