Inverse gating for low energy encryption

S. Banik, A. Bogdanov, F. Regazzoni, Takanori Isobe, Harunaga Hiwatari, T. Akishita
{"title":"Inverse gating for low energy encryption","authors":"S. Banik, A. Bogdanov, F. Regazzoni, Takanori Isobe, Harunaga Hiwatari, T. Akishita","doi":"10.1109/HST.2018.8383909","DOIUrl":null,"url":null,"abstract":"In this paper we explore the technique of “inverse gating” which is a significant improvement over the “round gating” technique introduced in HOST 2016. Round gating worked by generating timing signals to separate glitch propagation from one circuit element to the next. Inverse gating generates the same timing signals required to segregate transient round signals, in a manner that incurs less delay and hence lesser switching activity in the circuits. We also show that energy-wise, inverse gated circuits outperform round gated circuits by a margin of around 30 %. In the second part of the paper, we further explore the efficiency of the energy reduction by tuning some of the design parameters. The most natural candidate for this was the delay of the buffer used for creating the timing signals. We found that the optimal energy consumption for any round and inverse gated unrolled block cipher occurs at a particular range of this delay value. We try to explain the optimality of this particular choice of design parameter with the help of the implementation of the AES-128 block cipher.","PeriodicalId":6574,"journal":{"name":"2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","volume":"1 1","pages":"173-176"},"PeriodicalIF":0.0000,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HST.2018.8383909","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7

Abstract

In this paper we explore the technique of “inverse gating” which is a significant improvement over the “round gating” technique introduced in HOST 2016. Round gating worked by generating timing signals to separate glitch propagation from one circuit element to the next. Inverse gating generates the same timing signals required to segregate transient round signals, in a manner that incurs less delay and hence lesser switching activity in the circuits. We also show that energy-wise, inverse gated circuits outperform round gated circuits by a margin of around 30 %. In the second part of the paper, we further explore the efficiency of the energy reduction by tuning some of the design parameters. The most natural candidate for this was the delay of the buffer used for creating the timing signals. We found that the optimal energy consumption for any round and inverse gated unrolled block cipher occurs at a particular range of this delay value. We try to explain the optimality of this particular choice of design parameter with the help of the implementation of the AES-128 block cipher.
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低能加密的逆门控
在本文中,我们探索了“逆门控”技术,这是对HOST 2016中引入的“圆门控”技术的重大改进。圆门控的工作原理是产生定时信号,将故障从一个电路元件传播到下一个电路元件。反向门控产生与隔离瞬态圆信号所需的相同定时信号,以一种导致较少延迟的方式,从而减少电路中的开关活动。我们还表明,在能量方面,反向门控电路的性能比圆门控电路高出约30%。在论文的第二部分,我们进一步探讨了通过调整一些设计参数的节能效率。最自然的候选是用于创建定时信号的缓冲区的延迟。我们发现任何圆形和反向门控展开分组密码的最佳能量消耗发生在该延迟值的特定范围内。我们试图借助AES-128分组密码的实现来解释这种特定设计参数选择的最优性。
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