A 1.95 V, 0.34 mW 12-bit sigma-delta modulator stabilized by local feedback loops

Abstract

The design of a low power, low voltage, 12-bit 8 kHz bandwidth /spl Sigma//spl Delta/ modulator that achieves 0.34 mW power consumption at 1.95 V supply is described. The modulator employs a novel architecture in which a third-order modulator is stabilized by a local feedback loop around each integrator. Unlike multi-stage /spl Sigma//spl Delta/ modulators, this architecture is very tolerant to the modest DC gain of low voltage opamps. The architecture, together with special circuit techniques, permits a low voltage switched capacitor implementation at 1.95 V-3.3 V supply using standard 1.2 /spl mu/m CMOS technology.