Simulation of CMOS IO Standard Based Energy Efficient Gurmukhi Unicode Reader on FPGA

Abstract

In order to fill the research gap of energy efficient hardware design in natural language processing, this project reports the designing of an energy efficient Gurumukhi Unicode Reader on Field Programmable Gate Array (FPGA). To avoid transmission line reflection, a usual problem in hardware design, impedances of transmission line, device and port should be equal. In order to avoid transmission line reflection and make the design energy efficient too, we are using low voltage variants of CMOS: LVCMOS (Low Voltage Complementary Metal oxide Semiconductor) and TTL: LVTTL (Low Voltage Transistor Transistor Logic) I/O standards were used in this project. There is 58.33% and 58.97% decrease in IO power dissipation with LVCMOS12, in compare to LVCMOS25 for 625MHz and 1GHz respectively, with no significant changes in clock power, leakage power and junction temperature. This design is also tested on 25MHz, 125MHz and 25GHz operating frequency with four different LVCMOS.