A 12-bit 350-MS/s Pipelined ADC in 40-nm CMOS

Abstract

A 12-bit 350-MS/s pipelined Analog-to-Digital Converter (ADC) in 40-nm CMOS is presented in this paper. The architecture of 5 stages and 1 backend flash sub-ADC is chosen to ensure the completion of 12bit analog-to-digital conversion. The ADC leverages SHA-less constructure and appropriate sampling capacitors to reduce power consumption and setting errors. In order to fulfill gain and bandwidth requirements, a two-stage op-amp with miller compensation is designed and simulated. The direct current gain, poles and zeros of the amplifier are derived afterward. The results reveal that the ADC achieves a 10.07 bits ENOB and 70. S6dB SFDR at 350 MS/s sample rate. The layout occupies 0.1875 mm2 area and consumes 123 mW at 1.1-V supplies.