A 43.4μW photoplethysmogram-based heart-rate sensor using heart-beat-locked loop

D. Jang, Seonghwan Cho
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引用次数: 11

Abstract

Photoplethysmogram (PPG) sensors have gained great popularity in recent years as they can easily obtain heart rate (HR) in wearable devices such as smart watches and smart rings. However, one of the biggest problems for PPG sensors is their large power consumption, as wearable devices are highly limited in its battery capacity. The power consumption of a PPG sensor is typically dominated by the LED driver, which requires several to a few tens of mA of current. Thus, many previous works are aimed at reducing the LED driver power [1-5]. The most widely used method is duty-cycling the LED by using a train of discrete pulses instead of always turning on the LED [1-4]. As a PPG signal has low bandwidth, the duty-cycle ratio of the LED can be as low as 1%. Another low-power method is compressive sampling, which exploits the sparse nature of PPG signals [5]. Although it can reduce the effective duty-cycle ratio down to 0.0125%, a critical problem is that a large power consumption is required in reconstructing the compressive-sampled signal. In this work, we present an ultra-low-power PPG sensor with a heartbeat-locked loop (HBLL) that turns on the LED only during the PPG peaks and thus achieves an effective duty cycle of 0.0175%. We also reduce the power consumption of the analog front-end (AFE) by using the HBLL, which is in contrast to previous works where AFE power is not duty-cycled. A prototype implemented in 0.18μm CMOS demonstrates 43.4μW of total power consumption with less than 2.1bpm error in heart rate.
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一种基于43.4μW光电容积图的心率传感器,采用心跳锁定回路
近年来,Photoplethysmogram (PPG)传感器由于可以在智能手表和智能戒指等可穿戴设备中轻松获取心率(HR)而受到广泛欢迎。然而,PPG传感器最大的问题之一是其巨大的功耗,因为可穿戴设备的电池容量受到高度限制。PPG传感器的功耗通常由LED驱动器主导,它需要几到几十毫安的电流。因此,以前的许多工作都是为了降低LED驱动功率[1-5]。最广泛使用的方法是通过使用一列离散脉冲来占空比LED,而不是始终打开LED[1-4]。由于PPG信号具有低带宽,LED的占空比可低至1%。另一种低功耗方法是压缩采样,它利用了PPG信号的稀疏特性[5]。虽然它可以将有效占空比降低到0.0125%,但一个关键的问题是在重建压缩采样信号时需要很大的功耗。在这项工作中,我们提出了一种超低功耗PPG传感器,该传感器具有心跳锁定环(HBLL),仅在PPG峰值期间打开LED,从而实现0.0175%的有效占空比。我们还通过使用HBLL降低了模拟前端(AFE)的功耗,这与以前AFE功率不占空比的工作形成对比。在0.18μm CMOS上实现的样机显示,总功耗为43.4μW,心率误差小于2.1bpm。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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