Evgeny Bolotin, A. Morgenshtein, I. Cidon, R. Ginosar, A. Kolodny
{"title":"Automatic hardware-efficient SoC integration by QoS network on chip","authors":"Evgeny Bolotin, A. Morgenshtein, I. Cidon, R. Ginosar, A. Kolodny","doi":"10.1109/ICECS.2004.1399722","DOIUrl":null,"url":null,"abstract":"Efficient module integration in systems on chip (SoC) is a great challenge. We present a novel automated network on chip (NoC) centric integration method for large and complex SoCs. A quality of service NoC (QNoC) architecture and its design considerations are presented. Then, we describe a chain of design automation tools that allows fast and hardware-efficient SoC integration using the QNoC paradigm. The tool-chain receives a list of system modules and their inter-module communication requirements and results in complete system hardware and verification models for faster SoC fabrication and easier verification.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"46","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Giornale di Storia Costituzionale","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2004.1399722","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"Arts and Humanities","Score":null,"Total":0}
引用次数: 46
Abstract
Efficient module integration in systems on chip (SoC) is a great challenge. We present a novel automated network on chip (NoC) centric integration method for large and complex SoCs. A quality of service NoC (QNoC) architecture and its design considerations are presented. Then, we describe a chain of design automation tools that allows fast and hardware-efficient SoC integration using the QNoC paradigm. The tool-chain receives a list of system modules and their inter-module communication requirements and results in complete system hardware and verification models for faster SoC fabrication and easier verification.