Hardware implementation of the Haar 2D discrete wavelet transform with an application to image watermarking

Abstract

This paper presents a hardware implementation of the lifting 2D discrete wavelet transform of Haar for real-time image applications. The hardware architecture is designed using Xilinx System Generator software. Then, it is implemented on the FPGA-ZYNQ ZC 020 which results in low resources utilization and high performance. In FPGA-ZYNQ, the proposed hardware 2D DWT of Haar can achieve a frequency of 271.37 MHz with a throughput of 8683.84 Mbps. In addition, an application of the hardware lifting 2D DWT of Haar for image watermarking is presented. The algorithm inserts a binary watermark in the high-frequency band HL after two-level of the wavelet decomposition. The experimental results show good results.