R. Kim, B. H. Kim, J. N. Kim, J. J. Lee, J. Baek, J. Hwang, J. Hwang, J. Chang, S. Yoo, T. Yim, K. Chung, K. H. Park, T. Oszinda, I. S. Kim, E. Lee, S. Nam, S. Jung, Y. W. Cho, H. Choi, J. S. Kim, S. H. Ahn, S. H. Park, B. Yoon, J. Ku, S. Paak, N. Lee, S. Choi, H. Kang, E. Jung
{"title":"High performance Cu/low-k interconnect strategy beyond 10nm logic technology","authors":"R. Kim, B. H. Kim, J. N. Kim, J. J. Lee, J. Baek, J. Hwang, J. Hwang, J. Chang, S. Yoo, T. Yim, K. Chung, K. H. Park, T. Oszinda, I. S. Kim, E. Lee, S. Nam, S. Jung, Y. W. Cho, H. Choi, J. S. Kim, S. H. Ahn, S. H. Park, B. Yoon, J. Ku, S. Paak, N. Lee, S. Choi, H. Kang, E. Jung","doi":"10.1109/IITC-MAM.2015.7325599","DOIUrl":null,"url":null,"abstract":"CVD-Ru based reflow Cu scheme demonstrates robust gap fill performance at 10nm and 7nm node equivalent patterns. Potential EM and TDDB reliability concerns associated with Ru CMP are identified and successfully addressed by the application of new processes and materials. This suggests our proposed scheme can be one of promising candidates for 10nm node logic device and beyond.","PeriodicalId":6514,"journal":{"name":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","volume":"63 1","pages":"1-4"},"PeriodicalIF":0.0000,"publicationDate":"2015-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IITC-MAM.2015.7325599","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
CVD-Ru based reflow Cu scheme demonstrates robust gap fill performance at 10nm and 7nm node equivalent patterns. Potential EM and TDDB reliability concerns associated with Ru CMP are identified and successfully addressed by the application of new processes and materials. This suggests our proposed scheme can be one of promising candidates for 10nm node logic device and beyond.
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