SivaChandra Jangam, A. Bajwa, Kannan K Thankkappan, Premsagar Kittur, S. Iyer
{"title":"Electrical Characterization of High Performance Fine Pitch Interconnects in Silicon-Interconnect Fabric","authors":"SivaChandra Jangam, A. Bajwa, Kannan K Thankkappan, Premsagar Kittur, S. Iyer","doi":"10.1109/ECTC.2018.00197","DOIUrl":null,"url":null,"abstract":"The Silicon-Interconnect Fabric (Si-IF) is a highly scalable platform for heterogenous integration of dielets using a fine interconnect pitch (? 10 µm) and small inter-dielet spacing (? 100 µm) [1]. In our fine-pitch integration scheme, short links on Si-IF (? 500 µm) are used for inter-dielet communication, reducing the latency (? 35 ps) and energy /bit (? 0.04 pJ/b) [2]. In this paper, we demonstrate the excellent transfer characteristics of the Si-IF links, verified experimentally. The measured insertion loss in these short Si-IF links (? 500 µm) is ? 2 dB for frequencies up to 30 GHz. Further, the transfer characteristics show only a single pole, demonstrating an RC-link behavior. We show that assemblies on Si-IF have 16-25X lower parasitic inductance, and 6-40X lower parasitic capacitance compared to assemblies on interposers and PCBs. We illustrate that using the Simple Universal Parallel intERface for chips (SuperCHIPS) protocol [2] for data transfer, data rates of ? 10 Gbps/link are realizable at an energy/bit of ? 0.04 pJ/b. Subsequently, due to the high interconnect density, the overall bandwidth/mm is ? 8 Tbps/mm. This corresponds to an improvement of 120-300X in bandwidth/mm and a reduction of 100-500X in energy/bit compared to a conventional PCB-based integration.","PeriodicalId":6555,"journal":{"name":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"1283-1288"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"25","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 68th Electronic Components and Technology Conference (ECTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.2018.00197","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 25
Abstract
The Silicon-Interconnect Fabric (Si-IF) is a highly scalable platform for heterogenous integration of dielets using a fine interconnect pitch (? 10 µm) and small inter-dielet spacing (? 100 µm) [1]. In our fine-pitch integration scheme, short links on Si-IF (? 500 µm) are used for inter-dielet communication, reducing the latency (? 35 ps) and energy /bit (? 0.04 pJ/b) [2]. In this paper, we demonstrate the excellent transfer characteristics of the Si-IF links, verified experimentally. The measured insertion loss in these short Si-IF links (? 500 µm) is ? 2 dB for frequencies up to 30 GHz. Further, the transfer characteristics show only a single pole, demonstrating an RC-link behavior. We show that assemblies on Si-IF have 16-25X lower parasitic inductance, and 6-40X lower parasitic capacitance compared to assemblies on interposers and PCBs. We illustrate that using the Simple Universal Parallel intERface for chips (SuperCHIPS) protocol [2] for data transfer, data rates of ? 10 Gbps/link are realizable at an energy/bit of ? 0.04 pJ/b. Subsequently, due to the high interconnect density, the overall bandwidth/mm is ? 8 Tbps/mm. This corresponds to an improvement of 120-300X in bandwidth/mm and a reduction of 100-500X in energy/bit compared to a conventional PCB-based integration.