VLSI register, instruction and data caches suited to on chip CPU multi-threading support for real-time multi-media applications

Abstract

The architecture of a CPU capable of both executing multithreaded user processes in a commercial multi-threaded operating system environment and rapidly (sub microsecond) responding to real-time events, such as those that arise in the processing and synchronization of audio-video-data streams constituting concurrent interactive multi-media sessions, is discussed in this paper. The rapid, often simple, responses of a CPU to prioritized requests requires careful design of the on chip caches and registers and management of the hazards causing latencies in the CPU pipeline. The novel incorporation of a register cache in the CPU, its design, and the design of the instruction and data caches is described.