{"title":"Application of resist profile model and resist-etch model in solving 28nm metal resist toploss","authors":"Yiqun Tan, Weiwei Wu, Quan Chen, Shirui Yu","doi":"10.1109/CSTIC.2017.7919747","DOIUrl":null,"url":null,"abstract":"As critical dimensions decrease to 28 nm node and beyond, more etching failures are induced by the resist loss increases. Only two-dimensional (XY) contours are considered by traditional optical proximity correction (OPC) models, while vertical direction diffusion is neglected, resulting in inaccuracy in valuation of the resist loss. Rigorous resist simulators can simulate a three-dimensional (3-D) resist profile, but they are not fast enough for correction or verification on a full chip, which restrict their usage in technology development below 28nm node. However, for one hand, resist loss for positive-tone resists is mainly driven by optical intensity variations, which are accurately modeled by the optical portion of an OPC model. For the other, resist loss can be reflected by the quickly shrinking in process window condition. In this paper we show that a compact resist model can be used to determine resist loss by properly selecting the optical image plane for calibration or by introduction of CDs data after etching. Both these two models can be used to identify toploss hotspots on a full chip.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"26 1","pages":"1-3"},"PeriodicalIF":0.0000,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 China Semiconductor Technology International Conference (CSTIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSTIC.2017.7919747","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
As critical dimensions decrease to 28 nm node and beyond, more etching failures are induced by the resist loss increases. Only two-dimensional (XY) contours are considered by traditional optical proximity correction (OPC) models, while vertical direction diffusion is neglected, resulting in inaccuracy in valuation of the resist loss. Rigorous resist simulators can simulate a three-dimensional (3-D) resist profile, but they are not fast enough for correction or verification on a full chip, which restrict their usage in technology development below 28nm node. However, for one hand, resist loss for positive-tone resists is mainly driven by optical intensity variations, which are accurately modeled by the optical portion of an OPC model. For the other, resist loss can be reflected by the quickly shrinking in process window condition. In this paper we show that a compact resist model can be used to determine resist loss by properly selecting the optical image plane for calibration or by introduction of CDs data after etching. Both these two models can be used to identify toploss hotspots on a full chip.