Hyunggon Kim, Jungjune Park, Ki-Tae Park, Pansuk Kwak, O. Kwon, Chulbum Kim, Younyeol Lee, Sangsoo Park, Kyungmin Kim, Doohyung Cho, Juseok Lee, Jungho Song, Soowoong Lee, H. Yoo, Sanglok Kim, Seungwoo Yu, Sungjun Kim, Sungsoo Lee, K. Kyung, Yong Lim, C. Chung
{"title":"A 159mm2 32nm 32Gb MLC NAND-flash memory with 200MB/s asynchronous DDR interface","authors":"Hyunggon Kim, Jungjune Park, Ki-Tae Park, Pansuk Kwak, O. Kwon, Chulbum Kim, Younyeol Lee, Sangsoo Park, Kyungmin Kim, Doohyung Cho, Juseok Lee, Jungho Song, Soowoong Lee, H. Yoo, Sanglok Kim, Seungwoo Yu, Sungjun Kim, Sungsoo Lee, K. Kyung, Yong Lim, C. Chung","doi":"10.1109/ISSCC.2010.5433912","DOIUrl":null,"url":null,"abstract":"Providing both low cost and high storage capacity by means of device scaling and multi-level cell has been a fundamental feature in developing of NAND flash memory to meet an ever-growing flash market. Recently, however, a high speed interface like DDR (Double Data Rate) was newly adopted in NAND flash to satisfy the requirement of emerging market such as SSD (Solid-State Disk) application where high read and write throughputs are demanded [1]. In addition, as NAND scaling further, a portion of data loading and data out times in overall NAND flash performance has been increased due to increasing page size from 2K to 8K bytes, and even up to 16K bytes at two-plane operation. It significantly affects overall performance degradation in not only SSD but also conventional flash card system. The high speed interface in NAND flash, however, causes to increase chip size because of multiple memory planes more than two and additional signal buses [1]. Therefore, a high speed data interface capability with minimized chip size penalty is required in DDR NAND flash. This paper presents 159mm2 32Gb MLC NAND flash which is capable of 200MB/s read and 12MB/s write throughputs in a 32nm technology.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"8 1","pages":"442-443"},"PeriodicalIF":0.0000,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"21","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2010.5433912","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 21
Abstract
Providing both low cost and high storage capacity by means of device scaling and multi-level cell has been a fundamental feature in developing of NAND flash memory to meet an ever-growing flash market. Recently, however, a high speed interface like DDR (Double Data Rate) was newly adopted in NAND flash to satisfy the requirement of emerging market such as SSD (Solid-State Disk) application where high read and write throughputs are demanded [1]. In addition, as NAND scaling further, a portion of data loading and data out times in overall NAND flash performance has been increased due to increasing page size from 2K to 8K bytes, and even up to 16K bytes at two-plane operation. It significantly affects overall performance degradation in not only SSD but also conventional flash card system. The high speed interface in NAND flash, however, causes to increase chip size because of multiple memory planes more than two and additional signal buses [1]. Therefore, a high speed data interface capability with minimized chip size penalty is required in DDR NAND flash. This paper presents 159mm2 32Gb MLC NAND flash which is capable of 200MB/s read and 12MB/s write throughputs in a 32nm technology.