SystemC opportunities in chip design flow

Abstract

Moore's law predicts that the number of transistors in a system will double every 18 months. However, in order to take advantage of the chip technology progress, the same progress needs to be made in the chip design process. The paper focuses on the benefit of SystemC technology in order to close this gap. We present research done in the Intel Development Center (IDC) with Tel-Aviv University (TAU) and Jerusalem College of Technology (JCT). The research explores different usages of SystemC in design and verification flow, which includes soft system verification (early in the design flows), architecture tradeoffs and a flow of SystemC to gate-level flow.