K. Vandersmissen, F. Inoue, D. Velenis, Y. Li, D. Dictus, B. Frees, S. Van Huylenbroeck, M. Kondo, T. Seino, N. Heylen, H. Struyf, M. H. van der Veen
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引用次数: 3
Abstract
In this work, we present a cost effective Cu electroless (ELD-Cu) metallization scheme in which through-silicon vias (TSVs), can be scaled towards higher aspect ratios. We successfully integrated 30 nm ELD-Cu on 15 nm Ru in 3×50 μm TSVs on 300 mm wafer scale and found excellent electrical reliability. Cost calculations revealed the major impact of the implementation of the platable Ru liner material on the costs for the deposition and chemical mechanical polishing part of the TSV metallization. In addition, we demonstrated a complete TSV filling for the 3.5 nm ALD-Ru case and investigated different kinds of Cu electrodeposition chemistries and their influence on the presence of micro-voids in the TSVs.
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