{"title":"Soft-core embedded processor-based Built-In Self-Test of FPGAs: A case study","authors":"Bradley F. Dutton, C. Stroud","doi":"10.1109/DFT.2009.51","DOIUrl":null,"url":null,"abstract":"This paper presents the results of a case study which investigates the use of an embedded soft-core processor to perform Built-In Self-Test (BIST) of the logic resources in Xilinx Virtex-5 Field Programmable Gate Arrays (FPGAs). We show that the approach reduces the complexity of an external BIST controller and the number of external reconfigurations, making it particularly appealing for in-system testing of high-reliability and fault-tolerant systems with FPGAs. However, the overall test time is not improved due to an increase in the size of the required configuration files as a consequence of the inclusion of the softcore embedded processor logic, whose relative irregularity results in less effective compression of configuration data files.","PeriodicalId":6463,"journal":{"name":"2010 42nd Southeastern Symposium on System Theory (SSST)","volume":"1 1","pages":"313-317"},"PeriodicalIF":0.0000,"publicationDate":"2009-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 42nd Southeastern Symposium on System Theory (SSST)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFT.2009.51","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
This paper presents the results of a case study which investigates the use of an embedded soft-core processor to perform Built-In Self-Test (BIST) of the logic resources in Xilinx Virtex-5 Field Programmable Gate Arrays (FPGAs). We show that the approach reduces the complexity of an external BIST controller and the number of external reconfigurations, making it particularly appealing for in-system testing of high-reliability and fault-tolerant systems with FPGAs. However, the overall test time is not improved due to an increase in the size of the required configuration files as a consequence of the inclusion of the softcore embedded processor logic, whose relative irregularity results in less effective compression of configuration data files.