Factors affecting performance of CNT FET as a switch in memory cell

Abstract

As the world is on lookout for the smarter and faster and energy efficient technology, CNTFETs are considered as one of the emerging elements of nanotechnology for future logic applications, with high figures for mobility, achievable current density thereby creating high performance systems on chip with lower cost. CNTFETs are promising devices but what makes it difficult to model a CNT is that nanotubes have a very broad range of electronic, thermal, and structural properties that change depending on parameters defined by its diameter, length, gate parameters and chirality or twist. In this paper various device parameters are discussed which can affect the switching and storing of data in the CNTFET memory cells. Hysteresis was clearly observed in the curve of the drain current versus gate voltage, which makes the CNTFET possible for a nonvolatile memory cell. In this paper the various parameters which can affect the performance of CNT as memory cell has been discussed.