On-chip bandpass single-pole-double-throw switch based on multicoupled line

Jian-fong Wu, Yo-Shen Lin
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引用次数: 2

Abstract

An on-chip bandpass single-pole-double-throw (SPDT) switch with very compact circuit size is proposed, which is realized using a capacitvely loaded multicoupled line. By sharing the first resonator between the two signal paths and by replacing the quarter-wavelength impedance transformer in conventional designs with a J-inverter, the circuit size can be much reduced. In addition, the capacitive loading can help improve the spurious response such that a very wide upper stopband up to 10f0 can be achieved. Specifically, a third-order bandpass SPDT switch with a center frequency f0 of 5.5 GHz and a bandwidth of about 10% is realized in a commercial GaAs pHEMT process. The measured in-band insertion loss in the on state is better than 4 dB with a 30-dB upper stopband up to 55 GHz. The measured isolation in the off state is better than 30 dB from dc to 55 GHz. The chip size is 1.5 mm × 1 mm, which is only about 0.028λ0 × 0.018λ0 at f0.
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基于多耦合线路的片上带通单极双掷开关
提出了一种电路尺寸非常紧凑的片上带通单极双掷(SPDT)开关,该开关采用电容负载多耦合线实现。通过在两个信号路径之间共享第一个谐振器,以及用j型逆变器取代传统设计中的四分之一波长阻抗变压器,电路尺寸可以大大减小。此外,容性负载可以帮助改善杂散响应,从而可以实现高达10f0的非常宽的上阻带。具体而言,在商用GaAs pHEMT工艺中实现了中心频率为5.5 GHz、带宽约为10%的三阶带通SPDT开关。导通状态下测量的带内插入损耗优于4 dB,上阻带为30 dB,最高阻带为55 GHz。在直流至55 GHz范围内,在关断状态下测量到的隔离度优于30 dB。芯片尺寸为1.5 mm × 1mm,在f0时仅为0.028λ0 × 0.018λ0左右。
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