Read/Write Disturbance-Aware Design for MLC STT-RAM-based Cache

Abstract

Spin-transfer torque RAM (STT-RAM) has been considered as a promising candidate for the next generation on-chip last-level cache (LLC) due to its high cell density, non-volatility, and near-zero standby power. To further improve cell density, multi-level cell (MLC) STT-RAM has been proposed and widely adopted. However, applying MLC STT-RAM to LLC might suffer from both write disturbance (WD) and read disturbance (RD). WD that needs two-step write operations to write data in MLC STT-RAM cell incurs extra energy consumption and latency overhead. RD means that reading data from a cell will also disturb the original data. In this paper, we propose a read/write disturbance-aware (RWDA) design for MLC STT-RAM-based cache to reduce the overhead caused by the WD and RD. We delay restore operations to mitigate the adverse impacts of disturbances. Instead of the typical LRU replacement policy, we propose a priority-based victim selection policy to meet the very distinct characteristics of MLC STT-RAM. Since accessing soft bits is much more beneficial than accessing hard bits in terms of access latency and energy consumption, we adopt a swapping mechanism to exchange frequently accessed data from hard bits to soft bits. The experimental results showed that the proposed design could averagely achieve 26.6% energy-consumption reduction and 29.5% IPC of system-performance improvement, compared with the conventional design of MLC STT-RAM cache.