Wire planning for performance and yield enhancement

Abstract

In this paper, a wire planning strategy at the layout stage is proposed. The strategy addresses deep sub-micron (DSM) issues facing both designers and manufacturing engineers. For designers, the proposed method reduces the magnitude and variance of cross-coupling capacitance, making interconnect delay smaller and more predictable. For manufacturing engineers, the method reduces design sensitivity to random defects and process variations, thereby increasing yield. These objectives are achieved by directing commercial placement and routing tools to utilize routing resources more evenly over the entire die. Example implementations of the wire planning strategy are demonstrated.