Christopher M. Grotsch, B. Schoch, S. Wagner, I. Kallfass
{"title":"A Highly Linear FMCW Radar Chipset in H-Band with 50 GHz Bandwidth","authors":"Christopher M. Grotsch, B. Schoch, S. Wagner, I. Kallfass","doi":"10.1109/mwsym.2019.8700906","DOIUrl":null,"url":null,"abstract":"In this paper we present a transmit and receive MMIC for FMCW radar. The transmitter consisting of a frequency multiplier-by-three and a power amplifier featuring a high output power of 7 dBm with a 60 GHz 3-dB RF-bandwidth. The receiver is designed to be highly linear over a LO and RF bandwidth from 235 to 285 GHz. It employs a frequency tripler and a power amplifier as driver stage for a passive I/Q downconverter which enables an image reject architecture. To ensure linear operation and improve the overall receiver noise an input amplifier stage with an input referred 1-dB compression point exceeding -3 dBm is also integrated. The chipset is realized in a 35 nm metamorphic high electron mobility transistor technology.","PeriodicalId":6720,"journal":{"name":"2019 IEEE MTT-S International Microwave Symposium (IMS)","volume":"1 1","pages":"646-649"},"PeriodicalIF":0.0000,"publicationDate":"2019-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE MTT-S International Microwave Symposium (IMS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/mwsym.2019.8700906","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In this paper we present a transmit and receive MMIC for FMCW radar. The transmitter consisting of a frequency multiplier-by-three and a power amplifier featuring a high output power of 7 dBm with a 60 GHz 3-dB RF-bandwidth. The receiver is designed to be highly linear over a LO and RF bandwidth from 235 to 285 GHz. It employs a frequency tripler and a power amplifier as driver stage for a passive I/Q downconverter which enables an image reject architecture. To ensure linear operation and improve the overall receiver noise an input amplifier stage with an input referred 1-dB compression point exceeding -3 dBm is also integrated. The chipset is realized in a 35 nm metamorphic high electron mobility transistor technology.