Low power VLSI architecture of Viterbi scorer for HMM-based isolated word recognition

Abstract

HMM-based algorithms have been successfully applied to speech recognition since HMM provides a robust modeling capability of various speech signals and maintains high recognition accuracy. Viterbi scoring that searches the best matching word by comparing input utterance with reference speech models is a major task in HMM-based speech recognition. However, due to its operation complexity, Viterbi scoring is a significant source of power and computation when it is implemented by a dedicated VLSI architecture. This paper proposes a noble low power VLSI architecture of Viterbi scorer using modified Viterbi scoring procedure and precomputing logic. This method reduced power consumption by 20% and 27% for 100 and 400 candidate word recognition, respectively, compared with a conventional architecture at a cost of at most 12% increase in area due to additional control logics. As the device shrinks, power consumption becomes more significant than chip area.