Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996742
S. Alam, D. Troxel, C. Thompson
In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit are fabricated on different wafers, and then, the wafers are bonded with a glue layer of Cu or polymer based adhesive. Using our layout methodology, designers can layout such 3D circuits with necessary information on inter-wafer via/contact and orientation of each wafer embedded in the layout. We have implemented the layout methodology in 3DMagic. Availability of 3DMagic has led to interesting research with a wide range of layout-specific circuit analyses, from performance comparison of 2D and 3D circuits to layout-specific reliability analyses in 3D circuits. Using 3DMagic, researchers have designed and simulated an 8-bit encryption processor mapped into 2D and 3D FPGA layouts. Moreover, the layout methodology is an essential element of our ongoing research for the framework of a novel reliability computer aided design tool, ERNI-3D.
{"title":"A comprehensive layout methodology and layout-specific circuit analyses for three-dimensional integrated circuits","authors":"S. Alam, D. Troxel, C. Thompson","doi":"10.1109/ISQED.2002.996742","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996742","url":null,"abstract":"In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit are fabricated on different wafers, and then, the wafers are bonded with a glue layer of Cu or polymer based adhesive. Using our layout methodology, designers can layout such 3D circuits with necessary information on inter-wafer via/contact and orientation of each wafer embedded in the layout. We have implemented the layout methodology in 3DMagic. Availability of 3DMagic has led to interesting research with a wide range of layout-specific circuit analyses, from performance comparison of 2D and 3D circuits to layout-specific reliability analyses in 3D circuits. Using 3DMagic, researchers have designed and simulated an 8-bit encryption processor mapped into 2D and 3D FPGA layouts. Moreover, the layout methodology is an essential element of our ongoing research for the framework of a novel reliability computer aided design tool, ERNI-3D.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85932778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996777
S. Pillement, D. Chillet, O. Sentieys
Specifying virtual components at the behavioral level appears as the most promising solution to achieve a real efficiency of design reuse. In this paper we propose a methodology to specify and use Behavioral Level IP (BL-IP). Thus, IP designer tasks are easier due to the unified representation offered by this level of abstraction. The genericity of a behavioral IP permits efficient optimizations and make application context adaptations a reality We propose a unified framework to define an IP at the behavioral level and to tune a particular block according to designer needs. Therefore, we define the IP generator tool and the Universal High Level Synthesis concept.
{"title":"Behavioral IP specification and integration framework for high-level design reuse","authors":"S. Pillement, D. Chillet, O. Sentieys","doi":"10.1109/ISQED.2002.996777","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996777","url":null,"abstract":"Specifying virtual components at the behavioral level appears as the most promising solution to achieve a real efficiency of design reuse. In this paper we propose a methodology to specify and use Behavioral Level IP (BL-IP). Thus, IP designer tasks are easier due to the unified representation offered by this level of abstraction. The genericity of a behavioral IP permits efficient optimizations and make application context adaptations a reality We propose a unified framework to define an IP at the behavioral level and to tune a particular block according to designer needs. Therefore, we define the IP generator tool and the Universal High Level Synthesis concept.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81013569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996731
A. Kahng, S. Mantik
With advancing semiconductor technology and exponentially growing design complexities, predictability of design tools becomes an important part of a stable top-down design process. Prediction of individual tool solution quality enables designers to use tools to achieve best solutions within prescribed resources, thus reducing design cycle time. However, as EDA tools become more complex, they become less predictable. One factor in the loss of predictability is inherent noise in both algorithms and how the algorithms are invoked. In this work, we seek to identify sources of noise in EDA tools, and analyze the effects of these noise sources on design quality. Our specific contributions are: (i) we propose new behavior criteria for tools with respect to the existence and management of noise; (ii) we compile and categorize possible perturbations in the tool use model or tool architecture that can be sources of noise; and (iii) we assess the behavior of industry place and route tools with respect to these criteria and noise sources. While the behavior criteria give some guidelines for and characterize the stability of tools, we are not recommending that tools be immune from input perturbations. Rather, the categorization of noise allows us to better understand how tools will or should behave; this may eventually enable improved tool predictors that consider inherent tool noise.
{"title":"Measurement of inherent noise in EDA tools","authors":"A. Kahng, S. Mantik","doi":"10.1109/ISQED.2002.996731","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996731","url":null,"abstract":"With advancing semiconductor technology and exponentially growing design complexities, predictability of design tools becomes an important part of a stable top-down design process. Prediction of individual tool solution quality enables designers to use tools to achieve best solutions within prescribed resources, thus reducing design cycle time. However, as EDA tools become more complex, they become less predictable. One factor in the loss of predictability is inherent noise in both algorithms and how the algorithms are invoked. In this work, we seek to identify sources of noise in EDA tools, and analyze the effects of these noise sources on design quality. Our specific contributions are: (i) we propose new behavior criteria for tools with respect to the existence and management of noise; (ii) we compile and categorize possible perturbations in the tool use model or tool architecture that can be sources of noise; and (iii) we assess the behavior of industry place and route tools with respect to these criteria and noise sources. While the behavior criteria give some guidelines for and characterize the stability of tools, we are not recommending that tools be immune from input perturbations. Rather, the categorization of noise allows us to better understand how tools will or should behave; this may eventually enable improved tool predictors that consider inherent tool noise.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85445102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996725
A. Ilumoka
Recent ITRS predictions indicate that by the year 2011, the billion transistor monolithic die will be a reality. This clearly poses a challenge to gigascale integrated circuit design with regard to provision of multilevel interconnect wiring for the distribution of power, data and control signals to all parts of a chip. This paper addresses the problem of characterization, modeling and verification of 3D chip level interconnect crosstalk. The novel methodology proposed involves topological decomposition of interconnects into standard cells and the creation of parameterized models of these primitive structures using neural networks. Experimental results from a high performance operational amplifier demonstrates the viability of the approach.
{"title":"Chip level signal integrity analysis and crosstalk prediction using artificial neural nets","authors":"A. Ilumoka","doi":"10.1109/ISQED.2002.996725","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996725","url":null,"abstract":"Recent ITRS predictions indicate that by the year 2011, the billion transistor monolithic die will be a reality. This clearly poses a challenge to gigascale integrated circuit design with regard to provision of multilevel interconnect wiring for the distribution of power, data and control signals to all parts of a chip. This paper addresses the problem of characterization, modeling and verification of 3D chip level interconnect crosstalk. The novel methodology proposed involves topological decomposition of interconnects into standard cells and the creation of parameterized models of these primitive structures using neural networks. Experimental results from a high performance operational amplifier demonstrates the viability of the approach.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83830955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996728
A. Kahng, Gary Smith
The International Technology Roadmap for Semiconductors (ITRS) presents an industrywide consensus on the "best current estimate" of the industry's research and development needs out to a 15-year horizon. As such, it provides a guide to the efforts of companies, research organizations, and governments. The ITRS has improved the quality of R&D investment decisions made at all levels and has helped channel research efforts to areas that truly need research breakthroughs. The 2001 edition of ITRS is the result of a worldwide consensus building process. The participation of semiconductor experts from Europe, Japan, Korea, Taiwan, and the USA. has ensured that the 2001 ITRS continues to be the definitive source of guidance for semiconductor research as we strive to extend the historical advancement of semiconductor technology. This paper presents details of an important new element of the 2001 ITRS, namely, the design cost model that has been introduced in the design chapter.
{"title":"A new design cost model for the 2001 ITRS","authors":"A. Kahng, Gary Smith","doi":"10.1109/ISQED.2002.996728","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996728","url":null,"abstract":"The International Technology Roadmap for Semiconductors (ITRS) presents an industrywide consensus on the \"best current estimate\" of the industry's research and development needs out to a 15-year horizon. As such, it provides a guide to the efforts of companies, research organizations, and governments. The ITRS has improved the quality of R&D investment decisions made at all levels and has helped channel research efforts to areas that truly need research breakthroughs. The 2001 edition of ITRS is the result of a worldwide consensus building process. The participation of semiconductor experts from Europe, Japan, Korea, Taiwan, and the USA. has ensured that the 2001 ITRS continues to be the definitive source of guidance for semiconductor research as we strive to extend the historical advancement of semiconductor technology. This paper presents details of an important new element of the 2001 ITRS, namely, the design cost model that has been introduced in the design chapter.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90590090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996707
S. Koranne
Testing of embedded core based system-on-chip (SOC) ICs is a well known problem, and the upcoming IEEE P1500 (SECT) standard proposes DfT solutions to alleviate it. One of the proposals is to provide every core in the SOC with test access wrappers. Previous approaches to the problem of wrapper design have proposed static core wrappers, which are designed for a particular test access mechanism (TAM) width. We present the first report of a design of reconfigurable core wrappers. An automatic procedure for the creation of DfT required for reconfiguration using a graph theoretic representation of core wrappers is also presented. Our method is superior to previously published methods as it admits dynamic reconfiguration of core level scan access structures with little area and delay overhead. Using reconfigurable core wrappers the quality of the SOC test schedule can be improved. Theoretical analysis of the corresponding scheduling problem indicates that good approximate schedules can be achieved without significant computational effort.
{"title":"Design of reconfigurable access wrappers for embedded core based SOC test","authors":"S. Koranne","doi":"10.1109/ISQED.2002.996707","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996707","url":null,"abstract":"Testing of embedded core based system-on-chip (SOC) ICs is a well known problem, and the upcoming IEEE P1500 (SECT) standard proposes DfT solutions to alleviate it. One of the proposals is to provide every core in the SOC with test access wrappers. Previous approaches to the problem of wrapper design have proposed static core wrappers, which are designed for a particular test access mechanism (TAM) width. We present the first report of a design of reconfigurable core wrappers. An automatic procedure for the creation of DfT required for reconfiguration using a graph theoretic representation of core wrappers is also presented. Our method is superior to previously published methods as it admits dynamic reconfiguration of core level scan access structures with little area and delay overhead. Using reconfigurable core wrappers the quality of the SOC test schedule can be improved. Theoretical analysis of the corresponding scheduling problem indicates that good approximate schedules can be achieved without significant computational effort.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85377452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996748
S. Ozev, A. Orailoglu
High levels of design integration and increasing number of analog blocks within a system necessitate automated system-level analog test generation and fault simulation tools. We outline a methodology and toolset for specification-based automated test generation and fault simulation for analog circuits. Test generation is targeted at providing the highest coverage for each specified parameter. The flexibility of assigning analog test attributes is utilized for merging tests leading to test time reduction with no loss in test coverage. Further optimization in test time is obtained through fault simulations by selecting tests that provide adequate coverage in terms of several components and dropping the ones that do not provide additional coverage. The generated test set, fault and yield coverages in terms of each targeted parameter, and testability problems are reported by the tool.
{"title":"An integrated tool for analog test generation and fault simulation","authors":"S. Ozev, A. Orailoglu","doi":"10.1109/ISQED.2002.996748","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996748","url":null,"abstract":"High levels of design integration and increasing number of analog blocks within a system necessitate automated system-level analog test generation and fault simulation tools. We outline a methodology and toolset for specification-based automated test generation and fault simulation for analog circuits. Test generation is targeted at providing the highest coverage for each specified parameter. The flexibility of assigning analog test attributes is utilized for merging tests leading to test time reduction with no loss in test coverage. Further optimization in test time is obtained through fault simulations by selecting tests that provide adequate coverage in terms of several components and dropping the ones that do not provide additional coverage. The generated test set, fault and yield coverages in terms of each targeted parameter, and testability problems are reported by the tool.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78967242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996753
Mandeep Singh, I. Koren
The reliability of ADCs used in highly critical systems can be increased by applying a two-step procedure starting with sensitivity analysis followed by redesign. The sensitivity analysis is used to identify the most sensitive blocks which could then be redesigned for better reliability by incorporating fault tolerance. This paper illustrates the steps involved in incorporating fault tolerance in an ADC. Two redesign techniques to improve the reliability of a circuit are presented. Novel selective node resizing algorithms for increased tolerance against /spl alpha/-particle induced transients are discussed.
{"title":"Incorporating fault tolerance in analog-to-digital converters (ADCs)","authors":"Mandeep Singh, I. Koren","doi":"10.1109/ISQED.2002.996753","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996753","url":null,"abstract":"The reliability of ADCs used in highly critical systems can be increased by applying a two-step procedure starting with sensitivity analysis followed by redesign. The sensitivity analysis is used to identify the most sensitive blocks which could then be redesigned for better reliability by incorporating fault tolerance. This paper illustrates the steps involved in incorporating fault tolerance in an ADC. Two redesign techniques to improve the reliability of a circuit are presented. Novel selective node resizing algorithms for increased tolerance against /spl alpha/-particle induced transients are discussed.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88675349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996745
P. Bricaud
System-on-a-chip (SoC) is the paramount challenge of the electronic industry for the next millennium. The semiconductor industry has delivered what we were expecting and what was predicted: silicon availability for over 10 million gates. The VSIA (Virtual Socket Initiative Alliance) has defined industry standards and data formats for SoC. The reuse methodology manual, first 'how-to-do' book to create reusable IPs (intellectual properties) for SoC designs has been published. EDA tool providers understand the issues and are proposing new tools and solutions on a quarterly basis. The last stage needs to be run: consolidate the experience and know-how of VSIA and IP OpenMORE rating system into an industry adopted VC (virtual component) quality metrics, and then pursue to tackle the next challenges: formal system specifications and VC transfer infrastructure. The objective of this paper is to set the stage for the final step towards a VC quality metrics effort that the industry needs to adopt, and define the next achievable goals.
{"title":"VC rating and quality metrics: why bother? [SoC]","authors":"P. Bricaud","doi":"10.1109/ISQED.2002.996745","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996745","url":null,"abstract":"System-on-a-chip (SoC) is the paramount challenge of the electronic industry for the next millennium. The semiconductor industry has delivered what we were expecting and what was predicted: silicon availability for over 10 million gates. The VSIA (Virtual Socket Initiative Alliance) has defined industry standards and data formats for SoC. The reuse methodology manual, first 'how-to-do' book to create reusable IPs (intellectual properties) for SoC designs has been published. EDA tool providers understand the issues and are proposing new tools and solutions on a quarterly basis. The last stage needs to be run: consolidate the experience and know-how of VSIA and IP OpenMORE rating system into an industry adopted VC (virtual component) quality metrics, and then pursue to tackle the next challenges: formal system specifications and VC transfer infrastructure. The objective of this paper is to set the stage for the final step towards a VC quality metrics effort that the industry needs to adopt, and define the next achievable goals.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78598575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ISQED.2002.996710
Fulvio Corno, G. Cumani, M. Reorda, Giovanni Squillero
The paper addresses the issue of microprocessor and microcontroller testing, and follows an approach based on the generation of a test program. The proposed method relies on two phases: in the first, a library of code fragments (named macros) is generated by hand based on the knowledge of the instruction set, only. In the second phase, an optimization algorithm is run to suitably select macros and values for their parameters. The algorithm only relies on RT-level information, and exploits a suitable RT-level fault model to guide the test program generation. A major advantage of the proposed approach lies in the fact that it does not require any knowledge about the low level implementation of the processor. Experimental results gathered on an i8051 model using a prototypical implementation of the approach show that it is able to generate test programs whose gate-level fault coverage is higher than the one obtained by comparable gate-level ATPG tools, while the computational effort and the length of the generated test program are similar.
{"title":"Automatic test program generation from RT-level microprocessor descriptions","authors":"Fulvio Corno, G. Cumani, M. Reorda, Giovanni Squillero","doi":"10.1109/ISQED.2002.996710","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996710","url":null,"abstract":"The paper addresses the issue of microprocessor and microcontroller testing, and follows an approach based on the generation of a test program. The proposed method relies on two phases: in the first, a library of code fragments (named macros) is generated by hand based on the knowledge of the instruction set, only. In the second phase, an optimization algorithm is run to suitably select macros and values for their parameters. The algorithm only relies on RT-level information, and exploits a suitable RT-level fault model to guide the test program generation. A major advantage of the proposed approach lies in the fact that it does not require any knowledge about the low level implementation of the processor. Experimental results gathered on an i8051 model using a prototypical implementation of the approach show that it is able to generate test programs whose gate-level fault coverage is higher than the one obtained by comparable gate-level ATPG tools, while the computational effort and the length of the generated test program are similar.","PeriodicalId":20510,"journal":{"name":"Proceedings International Symposium on Quality Electronic Design","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85992886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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