{"title":"A 2.5-Gb/s clock recovery circuit for NRZ data in 0.4-/spl mu/m CMOS technology","authors":"S. Anand, B. Razavi","doi":"10.1109/CICC.2000.852690","DOIUrl":null,"url":null,"abstract":"This paper describes a 2.5-Gb/s phase-locked clock recovery circuit utilizing a two-stage ring oscillator and a sample-and-hold phase detector. Fabricated in a 0.4-/spl mu/m digital CMOS technology, the recovered clock exhibits an RMS jitter of 10.8 ps for a PRBS sequence of length 2/sup 7/-1 while dissipating 50 mW of power from a 3.3-V supply.","PeriodicalId":20702,"journal":{"name":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","volume":"77 1","pages":"379-382"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2000.852690","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper describes a 2.5-Gb/s phase-locked clock recovery circuit utilizing a two-stage ring oscillator and a sample-and-hold phase detector. Fabricated in a 0.4-/spl mu/m digital CMOS technology, the recovered clock exhibits an RMS jitter of 10.8 ps for a PRBS sequence of length 2/sup 7/-1 while dissipating 50 mW of power from a 3.3-V supply.
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