{"title":"A high-efficiency self-oscillating Class D amplifier in 0.35-um CMOS","authors":"Jun-Hong Weng, I-Chun Tsai, Y. Hsu","doi":"10.1109/ICCE-TW.2016.7520899","DOIUrl":null,"url":null,"abstract":"Consider the structure of a self-oscillation power amplifier as a power line driver. Self-oscillation power amplifier was improved by the Class-D power amplifier. The traditional Class-D switching power amplifier is vulnerable to distortion limitation. Due to the non-linear continuous time nature of the self-oscillation, it possesses peculiar properties that enable the construction of a highly linear, high-efficiency line driver. In the thesis which has efficiency up to 53%, SFDR and THD are 53.6 dB and 52.8 dB respectively. A prototype has been fabricated in a 0.35-um CMOS process to the proposed circuit.","PeriodicalId":6620,"journal":{"name":"2016 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW)","volume":"21 1","pages":"1-2"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCE-TW.2016.7520899","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Consider the structure of a self-oscillation power amplifier as a power line driver. Self-oscillation power amplifier was improved by the Class-D power amplifier. The traditional Class-D switching power amplifier is vulnerable to distortion limitation. Due to the non-linear continuous time nature of the self-oscillation, it possesses peculiar properties that enable the construction of a highly linear, high-efficiency line driver. In the thesis which has efficiency up to 53%, SFDR and THD are 53.6 dB and 52.8 dB respectively. A prototype has been fabricated in a 0.35-um CMOS process to the proposed circuit.
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