A Mixed Verification Strategy Tailored for Networks on Chip

Abstract

This paper targets the development of a verification methodology for Networks on Chip. We advocate the use of formal methods to guarantee an unambiguous expression of the specifications. A previous theorem proving based solution enables the verification of high-level properties for NoC communication algorithms, it deliberately addresses abstract NoC descriptions and ignores implementation details. We suggest here a complementary approach, oriented toward Assertion-Based Verification, that focuses on the verification of RT level implementations, also applicable to the on-line checking of robustness properties.