{"title":"Low latency check node unit architecture for nonbinary LDPC decoding","authors":"Huyen Thi Pham, Hanho Lee","doi":"10.1109/APCCAS.2016.7803986","DOIUrl":null,"url":null,"abstract":"This paper proposes a novel forward-backward four-way merger min-max algorithm and low latency check node unit (CNU) architecture for check node processing of nonbinary low-density parity check (NB-LDPC) codes. This algorithm derives simultaneously two output vectors for forward and backward processing in each step. A parallel switch network and parallel-serial elementary computation unit are proposed. Then, the CNU architecture corresponding to the algorithm is designed. The analysis and synthesis results show that the proposed CNU architecture obtains a latency reduction of 82.58% and 49.75% for any code rate without any loss performance, compared to previous works.","PeriodicalId":6495,"journal":{"name":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.2016.7803986","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper proposes a novel forward-backward four-way merger min-max algorithm and low latency check node unit (CNU) architecture for check node processing of nonbinary low-density parity check (NB-LDPC) codes. This algorithm derives simultaneously two output vectors for forward and backward processing in each step. A parallel switch network and parallel-serial elementary computation unit are proposed. Then, the CNU architecture corresponding to the algorithm is designed. The analysis and synthesis results show that the proposed CNU architecture obtains a latency reduction of 82.58% and 49.75% for any code rate without any loss performance, compared to previous works.