Low latency check node unit architecture for nonbinary LDPC decoding

Huyen Thi Pham, Hanho Lee
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Abstract

This paper proposes a novel forward-backward four-way merger min-max algorithm and low latency check node unit (CNU) architecture for check node processing of nonbinary low-density parity check (NB-LDPC) codes. This algorithm derives simultaneously two output vectors for forward and backward processing in each step. A parallel switch network and parallel-serial elementary computation unit are proposed. Then, the CNU architecture corresponding to the algorithm is designed. The analysis and synthesis results show that the proposed CNU architecture obtains a latency reduction of 82.58% and 49.75% for any code rate without any loss performance, compared to previous works.
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非二进制LDPC解码的低延迟检查节点单元体系结构
针对非二进制低密度奇偶校验(NB-LDPC)码的校验节点处理,提出了一种新颖的前向向后四向合并最小-最大算法和低延迟校验节点单元(CNU)架构。该算法在每一步中同时导出两个输出向量,分别用于向前和向后处理。提出了一种并行交换网络和并行串行初等计算单元。然后,设计了与算法相对应的CNU体系结构。分析和综合结果表明,与以往的工作相比,在任何码率下,所提出的CNU架构的延迟分别降低了82.58%和49.75%,而性能没有损失。
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