400 Gbps 2-Dimensional Optical Receiver Assembled on Wet Etched Silicon Interposer

Chenhui Li, R. Stabile, F. Kraemer, Teng Li, O. Raz
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引用次数: 3

Abstract

In this paper, based on a wet etched silicon interposer, we propose a 2.5D assembly of two dimensional optical transceivers for 400 Gbps parallel optical interconnections. In this opto-electronic packaging, two dimensional optical matrix is formed as 250 µm in both the x -and y-directions by exploiting commercial opto-electronic arrays, and a compact optical interface is used to couple the light channels with fiber ribbons. Each quadrant of the optical matrix is connected with its CMOS IC part via impedance matched co-planner wave guides. The shortest traces between optics and CMOS ICs can be 300 µm, benefiting from flip-chip technology. The process flow of silicon interposer fabrication is illustrated. With flip-chip bonding, 25 Gbps 2D 16-channel receiver is assembled on the silicon interposer, and the sub-module, including the optical interface, is scaled down to 4 mm by 6 mm. In addition, the performance of this assembled module is fully characterized. Uniform and clear eye patterns are captured for all of the channels. Receiver sensitivities are also tested for all channels at 25.78 Gbps, 2 31-1 PRBS, with the variation less than 1.5 dB at error free operation.
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基于湿蚀刻硅中间层的400gbps二维光接收机
在本文中,我们提出了一种基于湿蚀刻硅中间层的2.5D二维光收发器组件,用于400gbps并行光互连。在该光电封装中,利用商用光电阵列在x和y方向上形成250µm的二维光矩阵,并使用紧凑的光接口将光通道与光纤带耦合。光学矩阵的每个象限通过阻抗匹配的共规划波导与其CMOS IC部分连接。得益于倒装芯片技术,光学器件和CMOS ic之间的最短走线可达300µm。阐述了硅中间层的制造工艺流程。通过倒装片键合,将25gbps 2D 16通道接收器组装在硅中间层上,子模块(包括光接口)缩小到4mm × 6mm。此外,还充分表征了该组装模块的性能。统一和清晰的眼模式被捕获的所有通道。在25.78 Gbps, 2 31-1 PRBS下测试了所有信道的接收机灵敏度,在无误差操作下变化小于1.5 dB。
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