VLSI design of a priority arbitrator for shared buffer ATM switches

Abstract

Priority arbitration is an essential part of the ATM switches in order to support the integration of telecommunication services with difference characteristics. Service priority control selects the connection to output a cell among all connections destined to the same output port. Discard priority control selects the connection to discard a cell when the shared buffer is full. In this paper we present a VLSI design of a priority arbitrator for shared buffer ATM switches. This priority arbitrator is targeted to support our new service priority control scheme, reactive bandwidth arbitration (RBA), and new discard priority control scheme, local pushout discarding (LPD). The priority arbitrator is designed for an 8/spl times/8 shared buffer ATM switch with four priority classes per port and a link rate of 622 Mbps. The chip has 130 k gates in a chip area of 137.88 mm/sup 2/ using 0.6 /spl mu/m CMOS technology.