A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS

Abstract

ADC-based CDRs take digital samples of the received signal to recover the clock and data. Digital representation of the signal allows for extensive channel equalization in the digital domain. Recently-reported ADC-based CDRs sample the signal at 1× or 2× the baud rate. The 1× CDR aligns the sampling clock with the signal using a phase-tracking feedback loop [1–2], which requires a voltage-controlled oscillator or phase interpolator, both analog circuits, to adjust the phase of the sampling clock. To eliminate these analog circuits (and their phase control) in favor of an all-digital implementation, a blind-sampling ADC-based CDR (top of Fig. 8.6.1) samples the received signal at 2× without phase locking to the signal. The CDR then interpolates between the blind samples to obtain a new set of samples in order to recover the phase and data [3–4]. The doubling of the sampling rate, however, increases the ADC power consumption or, equivalently, reduces the maximum baud rate due to the conversion-rate limitations of ADCs.