Integrated circuit ESD protection structure failure analysis based on TLP technique

Abstract

This paper introduces an evaluation method of integrated circuit port protection structure burn-out mechanism basing on transmission line pulse test (TLP). Based on the analysis of a variety of typical ESD protection circuit structures of integrated circuit, the design procedure of TLP test scheme is provided. By establishing functional relation between I/V characteristic curves and the ESD damage failure of protection circuit, the level and consequence of integrated circuit ESD failure can be quantified precisely, the root causes also can be confirmed. With a failure analysis case of a typical clamp protection structure of 0.18μm process verifies the feasibility of the technique.