Warpage Tuning Study for Multi-chip Last Fan Out Wafer Level Package

Hung-Yuan Li, Allen Chen, S. Peng, George Pan, Stephen Chen
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引用次数: 11

Abstract

In recent years, the IoT popularity pushes the package development of 3C products into a more functional and thinner target. For high I/O density and low cost considered package, the promising Fan-out Wafer Level Packaging (FOWLP) provides a solution to match OSAT existing capability, besides, the chip last process in FOWLP can further enhance the total yield by selectable known-good dies (KGDs). However, under processing, the large portion of molding compound induces high warpage to challenge fabrication limitation. The additional leveling process is usually applied to lower the warpage that caused by the mismatch of coefficient of thermal expansion and Young's modulus from carriers, dies, and molding compound. This process results in the increase of package cost and even induce internal damages that affect device reliability. In order to avoid leveling process and improve warpage trend, in this paper, we simulated several models with different design of molding compound and dies, and then developed a multi-chip last FOWLP test vehicle by package dimension of 12x15 mm2 with 8x9 and 4x9 mm2 multiple dies, respectively. The test vehicle performed three redistribution layers (RDLs) including one fine pitch RDL of line width/line spacing 2um/2um, which is also the advantage of multi-chip last FOWLP, and also exhibited ball on trace structure for another low cost option. For the wafer warpage discussion, the results showed that tuning the thickness of molding compound can improve warpage trend, especially in the application of high modulus carrier, which improved wafer warpage within 1mm, for package warpage discussion, the thinner die can lower the warpage of package. Through well warpage controlling, the multi-chip last FOWLP package with ball on trace design was successfully presented in this paper, and also passed the package level reliability of TCB 1000 cycles, HTSL 1000 hrs, and uHAST 96 hrs, and drop test by board level reliability.
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多片最后扇出晶圆级封装翘曲调谐研究
近年来,物联网的普及将3C产品的封装发展推向了更多功能、更轻薄的目标。对于高I/O密度和低成本的封装,扇出晶圆级封装(FOWLP)提供了一种与OSAT现有能力相匹配的解决方案,此外,FOWLP中的芯片最后工艺可以通过可选的已知好芯片(KGDs)进一步提高总产量。然而,在加工过程中,大量成型化合物引起高翘曲,挑战了制造限制。附加的调平过程通常用于降低由载体、模具和成型化合物的热膨胀系数和杨氏模量不匹配引起的翘曲。这个过程会导致封装成本的增加,甚至会导致内部损坏,影响设备的可靠性。为了避免调平过程,改善翘曲趋势,本文对不同成型材料和模具设计的几种模型进行了仿真,然后分别采用8 × 9和4 × 9 mm2的多模封装尺寸为12 × 15 mm2的多芯片最后一辆FOWLP试验车。测试车采用了三层再分配层(RDL),其中一层线宽/线间距为2um/2um的细间距RDL,这也是多芯片最后一种FOWLP的优势,同时也展示了球在迹结构,这是另一种低成本的选择。对于晶圆翘曲的讨论,结果表明,调整成型化合物的厚度可以改善翘曲趋势,特别是在高模量载体的应用中,将晶圆翘曲改善在1mm以内;对于封装翘曲的讨论,更薄的模具可以降低封装的翘曲。本文通过井翘曲控制,成功地设计了多芯片最后一种带球在迹的FOWLP封装,并通过了TCB 1000次、HTSL 1000小时、uHAST 96小时的封装级可靠性测试和板级可靠性的跌落测试。
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