Analysis of cross-talk effects on logic cell delays in CMOS integrated circuits

Abstract

Shows how crosstalk coupling between signals with concurrent transitions can cause a significant increase in or a reduction of the propagation delay of CMOS logic cells connected to them. A reduced model for parasitic capacitive coupling is proposed, and the influence of electrical cell parameters on the internal delay is evaluated. As an application example, the authors analyze how an enlarged delay due to crosstalk can cause permanent logic faults in RS latch circuits.<>