{"title":"An Optimal Design of 2DoF FOPID/PID Controller using Non-symmetrical Optimum Principle for an AVR System with Time Delay","authors":"Marko Č. Bošković, T. Šekara, M. Rapaić","doi":"10.1109/INFOTEH53737.2022.9751259","DOIUrl":null,"url":null,"abstract":"In the present study, an optimization technique is performed to obtain optimal parameters of the fractional-order FOPID/PID controller for an automatic voltage regulator (AVR) system with the time delay introduced by measurement devices and communication links for data transfer. The primary aim of the controller design for AVR system is to sustain the terminal voltage of the synchronous generator (SG) within admissible ranges by adjusting exciter signals. The set of adjustable parameters of FOPID/PID controller is obtained through the maximization of the integral gain of FOPID controller under constraints on desired phase margin and two requirements on the basis of the non-symmetrical optimum principle. Resulting quality of the regulation is assessed with performance indices: settling time, overshoot and rise time, while Integral of the Absolute Error (IAE) is used as indicator of load disturbance rejection.","PeriodicalId":6839,"journal":{"name":"2022 21st International Symposium INFOTEH-JAHORINA (INFOTEH)","volume":"1 1","pages":"1-6"},"PeriodicalIF":0.0000,"publicationDate":"2022-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 21st International Symposium INFOTEH-JAHORINA (INFOTEH)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/INFOTEH53737.2022.9751259","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In the present study, an optimization technique is performed to obtain optimal parameters of the fractional-order FOPID/PID controller for an automatic voltage regulator (AVR) system with the time delay introduced by measurement devices and communication links for data transfer. The primary aim of the controller design for AVR system is to sustain the terminal voltage of the synchronous generator (SG) within admissible ranges by adjusting exciter signals. The set of adjustable parameters of FOPID/PID controller is obtained through the maximization of the integral gain of FOPID controller under constraints on desired phase margin and two requirements on the basis of the non-symmetrical optimum principle. Resulting quality of the regulation is assessed with performance indices: settling time, overshoot and rise time, while Integral of the Absolute Error (IAE) is used as indicator of load disturbance rejection.