Interconnect Technology Development for 180GHz Wireless mm-Wave System-in-Foil Transceivers

K. Nieweglowski, Patrick Seiler, D. Fritsche, Sebastian Lüngen, D. Plettemeier, C. Carta, F. Ellinger, K. Bock
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引用次数: 2

Abstract

In this work, a polyimide (PI) foil-based wireless transceiver, which can be placed on the top of each node chip stack, is proposed. The transceivers with Butler matrix (BM) steered antenna arrays enable directed links from each node on one PCB towards any other node on the neighboring board in the rack. These passive components can be integrated into the foil whereas the active components (mm-wave ICs – MMICs) fabricated in SiGe-technology have to be connected with low parasitic, matched (wave impedance) interconnects. First the development of fabrication of low-loss transmission line structures on PI-foils will be described. The technology is based on foils with 50µm PI-thickness with Cr/Cu seed metallization and galvanic thickened Au layer. This allows for precise definition of coplanar transmission lines with low roughness (RMS roughness of 20-530nm). The measurements of characteristic parameters show good agreement with simulated data – the deviation of parasitic components (L and C) is below than 10%. A transmission loss of about 0.5 dB/cm at 60 GHz and about 1 dB/cm at 200 GHz has been measured. These substrates have been used for flip-chip assembly of chip components in order to characterize the performance of FC-interconnect at frequencies up to 220 GHz. For this analysis test-chips with transmission lines fabricated in a 130 nm SiGe-BiCMOS technology have been used. In order to mount these chips with Al pad finish on the PI-foil substrates Au studbumps with reduced size (50µm diameter on foot and 30µm height) and thermosonic flip-chip bonding have been used. From the measurements of FC bonded test chips with µ-strip lines on the PI-foils a FC-interconnect loss of about 0.28 ± 0.05 dB per bump at 60 GHz and of about 0.73 ± 0.14 dB per bump at 200 GHz could be derived.
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180GHz无线毫米波系统箔收发器互连技术的发展
在这项工作中,提出了一种基于聚酰亚胺(PI)箔的无线收发器,可以放置在每个节点芯片堆栈的顶部。具有巴特勒矩阵(BM)定向天线阵列的收发器可以实现从PCB上的每个节点到机架中相邻板上的任何其他节点的定向链接。这些无源元件可以集成到箔片中,而采用sige技术制造的有源元件(毫米波ic - mmic)必须通过低寄生、匹配(波阻抗)互连连接。首先介绍了在pi箔上制造低损耗传输线结构的研究进展。该技术基于pi厚度为50 μ m的金属箔,采用Cr/Cu种子金属化和电镀锌增厚的Au层。这样可以精确定义低粗糙度的共面传输线(RMS粗糙度为20-530nm)。特征参数的测量结果与模拟数据吻合良好,寄生分量(L和C)的偏差小于10%。在60 GHz和200 GHz下的传输损耗分别约为0.5 dB/cm和1 dB/cm。这些衬底已用于芯片组件的倒装组装,以表征频率高达220 GHz的fc互连性能。为此,采用了130纳米SiGe-BiCMOS技术制造的传输线测试芯片。为了在pi箔衬底上安装这些带有Al衬底的芯片,使用了尺寸减小的Au凸点(脚上直径50 μ m,高度30 μ m)和热超声倒装芯片键合。通过在pi箔上使用微带线对FC键合测试芯片的测量,可以得出在60 GHz时FC互连损耗约为0.28±0.05 dB / bump,在200 GHz时FC互连损耗约为0.73±0.14 dB / bump。
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