A 900 MHz, 2.5 mA CMOS frequency synthesizer with an automatic SC tuning loop

Abstract

A 900 MHz PLL frequency synthesizer implemented in 0.6 /spl mu/m CMOS technology is developed for WINS (Wireless Integrated Network Sensors) applications. It incorporates an automatic SC discrete-tuning loop to extend the frequency tuning range to 20% while the VCO gain from the CMOS varactor continuous-tuning is kept low at only 20 MHz/V, to minimize the reference spurs. This frequency synthesizer achieves a phase noise of -102 dBc/Hz at 100 kHz offset and reference spurs below -55 dBc. The synthesizer, including an on-chip VCO, dissipates only 2.5 mA from a 3 V supply.